bbracker
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2611d214a6
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testbench update b/c QEMU extends 32b CSRs to 64b
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2021-06-20 09:24:19 -04:00 |
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bbracker
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7aa2f0d953
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make xCOUNTEREN what buildroot expects it to be
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2021-06-20 09:22:31 -04:00 |
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bbracker
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6e9c6e3e6a
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whoops wavedo typo
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2021-06-20 05:36:54 -04:00 |
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bbracker
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9469367da3
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make buildroot ignore SSTATUS because QEMU did not originally log it
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2021-06-20 05:31:24 -04:00 |
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bbracker
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78f4703dc9
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MSTATUS workaround
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2021-06-20 04:48:09 -04:00 |
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bbracker
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927d99cf3b
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workaround for ignoring MTIME
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2021-06-20 02:26:39 -04:00 |
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bbracker
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52fb630379
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remove lingering busybear stuff from buildroot do files
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2021-06-20 00:50:53 -04:00 |
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bbracker
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124ef980e3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-20 00:40:44 -04:00 |
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bbracker
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3e32ba3684
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make buildroot waves only turn on after a user-specified point
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2021-06-20 00:39:30 -04:00 |
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Ross Thompson
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bb756849a7
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Revert "Icache now uses physical lenght bits rather than XLEN."
This reverts commit d4de8a54a2.
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2021-06-19 08:58:34 -05:00 |
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Ross Thompson
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e4c932265d
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Revert "Improved some names in icache."
This reverts commit 22ea801edb.
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2021-06-19 08:58:32 -05:00 |
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bbracker
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ebe893b70c
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change buildroot config to use relative path for testvectors
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2021-06-18 22:28:07 -04:00 |
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bracker
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3d99c9c2c4
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gitignore merge
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2021-06-18 21:12:05 -05:00 |
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bracker
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ed75172f21
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handle tera usernames more gracefully
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2021-06-18 21:11:14 -05:00 |
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bbracker
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10ca2ac5bc
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on-Tera solution for sym linking to linux testvectors
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2021-06-18 22:01:18 -04:00 |
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bracker
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a9f9ef1180
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-18 20:41:01 -05:00 |
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bracker
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8a8b0dcfd7
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script support for copying large files from tera
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2021-06-18 20:40:19 -05:00 |
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Kip Macsai-Goren
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20c8e6d929
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fixed trap handler, maker errors, pagetables still need work.
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2021-06-18 18:13:08 -04:00 |
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Kip Macsai-Goren
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5e3f2ce5d5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-18 18:08:07 -04:00 |
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bbracker
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f394b91515
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-18 17:37:49 -04:00 |
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bbracker
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f84a689c19
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fixed PCtext error by using blocking assignments
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2021-06-18 17:37:40 -04:00 |
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Kip Macsai-Goren
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2117162a47
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-18 13:27:10 -04:00 |
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Ross Thompson
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0250d52ae3
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-06-18 12:24:42 -05:00 |
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Ross Thompson
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22ea801edb
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Improved some names in icache.
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2021-06-18 12:22:41 -05:00 |
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Ross Thompson
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d4de8a54a2
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Icache now uses physical lenght bits rather than XLEN.
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2021-06-18 12:02:59 -05:00 |
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David Harris
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43bc17350b
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Restored wally-busybear testbench now that graphical sim is working
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2021-06-18 12:36:25 -04:00 |
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bbracker
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958f60c704
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restore graphical buildroot sim
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2021-06-18 11:58:16 -04:00 |
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Abe
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892c14430b
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Updated directory coremark_bare's wally-config file to define PMP_ENTRIES
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2021-06-18 11:46:25 -04:00 |
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Kip Macsai-Goren
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a47519df27
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-18 10:46:43 -04:00 |
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bbracker
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1e93bbd119
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-18 09:49:37 -04:00 |
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bbracker
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72f1e3eab6
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buildroot added to regression because it passes regression
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2021-06-18 09:49:30 -04:00 |
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David Harris
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21a55458ca
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Made MemPAdrM and related signals PA_BITS wide
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2021-06-18 09:36:22 -04:00 |
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David Harris
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a3f3533cce
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Changed physical addresses to PA_BITS in size in MMU and TLB
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2021-06-18 09:11:31 -04:00 |
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bbracker
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0980ce92bc
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-18 08:15:40 -04:00 |
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bbracker
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8ae333a6b2
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remove unused testbench-busybear.sv
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2021-06-18 08:15:19 -04:00 |
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David Harris
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cc78504ae4
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Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX
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2021-06-18 08:13:15 -04:00 |
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David Harris
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72d8d34e3c
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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e03912f64c
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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David Harris
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8357b14957
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Further cleaning of PMA checker
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2021-06-17 22:27:39 -04:00 |
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Kip Macsai-Goren
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dd256acf53
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-17 21:41:15 -04:00 |
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David Harris
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91a13999a9
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Added SUPPORTED to each peripheral in each config file
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2021-06-17 21:36:32 -04:00 |
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David Harris
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54d9147c12
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-17 18:54:46 -04:00 |
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David Harris
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5e7ed4bd88
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added inputs to pmaadrdec
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2021-06-17 18:54:39 -04:00 |
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David Harris
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09c5e27853
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Started simplifying PMA checker
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2021-06-17 16:28:06 -04:00 |
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Abe
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985b08c7d1
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Commit message
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2021-06-17 14:49:13 -04:00 |
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Kip Macsai-Goren
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f16742bfe4
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removed old page table, test data read not working
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2021-06-17 13:48:16 -04:00 |
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Kip Macsai-Goren
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39bc39f691
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-17 12:17:13 -04:00 |
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bbracker
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076469230f
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added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version
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2021-06-17 12:09:10 -04:00 |
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bbracker
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db0abfd36d
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enable TIME CSR for 32 bit mode as well
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2021-06-17 11:34:16 -04:00 |
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bbracker
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7d1469a06c
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provide time and timeh CSRs based on CLINT's counter
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2021-06-17 08:38:30 -04:00 |
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