13 Commits

Author	SHA1	Message	Date
David Harris	6966554ee8	Fixed bug with CSRRS/CSRRC for MIP/SIP	2022-04-03 20:18:25 +00:00
Ross Thompson	5ef6cde52e	Added more ILA signals.	2022-04-02 16:39:45 -05:00
bbracker	54b9745a75	big interrupts refactor	2022-03-30 13:22:41 -07:00
bbracker	9f60256f22	1st attempt at multiple channel PLIC	2022-03-24 17:08:10 -07:00
David Harris	aa990be959	removed csrn and all of its outputs because depricated	2022-02-15 19:59:29 +00:00
David Harris	ed8ac3d881	Just needed to recompile - all good. Now removed uretM because N-mode is depricated	2022-02-15 19:48:49 +00:00
David Harris	5ef8f6bc7e	Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.	2022-02-15 19:20:41 +00:00
Ross Thompson	ec44774c77	Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv	2022-01-20 16:39:54 -06:00
Ross Thompson	5cf686429d	Merged in the debug ila updates.	2022-01-18 17:29:21 -06:00
Ross Thompson	fdc17f5017	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
Ross Thompson	55456e465c	Added icache access and icache miss to performance counters.	2022-01-09 22:56:56 -06:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00