Ross Thompson
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8d88ef93bc
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Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop.
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2023-07-28 11:20:29 -05:00 |
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Ross Thompson
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0e22fe5231
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Removed QEMU from configurations.
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2023-07-19 10:23:55 -05:00 |
|
Ross Thompson
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20751790f6
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Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.
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2023-07-14 16:31:44 -05:00 |
|
David Harris
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45667c9f4d
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Clean up privilege rs1 decoding and implement svinval as sfence.vma
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2023-07-13 02:41:17 -07:00 |
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David Harris
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c91bbc3ca8
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MENVCFG only exists if U_SUPPORTED
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2023-07-09 18:25:07 -07:00 |
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David Harris
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74a573cedd
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Removed outdated commment about endianness
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2023-07-06 12:41:46 -07:00 |
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David Harris
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29e62f05a4
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Removed MTINST, which is not used in a system without a hypervisor
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2023-07-06 12:40:53 -07:00 |
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David Harris
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6a88ac28e4
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Fixed csr typos
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2023-07-02 02:01:40 -07:00 |
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David Harris
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96477a4879
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Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode
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2023-07-02 02:00:27 -07:00 |
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David Harris
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e2708534cd
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Added environment configuration control (menvcfg/senvcfg) of cbo instructions
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2023-07-02 01:52:25 -07:00 |
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David Harris
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4d1ddd0c91
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Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations
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2023-07-02 00:34:30 -07:00 |
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Harshini Srinath
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e0a30ecc22
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Merge branch 'main' into main
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2023-06-14 11:52:45 -07:00 |
|
Harshini Srinath
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629ccb191f
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Update csrs.sv
Program clean up
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2023-06-13 22:16:43 -07:00 |
|
Harshini Srinath
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49c84f888f
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Update csrm.sv
Program clean up
|
2023-06-13 22:08:06 -07:00 |
|
Harshini Srinath
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aff15a0a46
|
Update csrc.sv
Program clean up
|
2023-06-13 21:54:47 -07:00 |
|
Harshini Srinath
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fb019a736c
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Update csr.sv
Program clean up
|
2023-06-13 21:12:49 -07:00 |
|
Harshini Srinath
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475e11e03f
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Update trap.sv
Program clean up
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2023-06-12 20:31:44 -07:00 |
|
Harshini Srinath
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e2af1fabd2
|
Update privmode.sv
Program clean up
|
2023-06-12 20:27:48 -07:00 |
|
Harshini Srinath
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ac7043770d
|
Update privileged.sv
Program clean up
|
2023-06-12 20:26:07 -07:00 |
|
Harshini Srinath
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5f7fe5619b
|
Update csru.sv
Program clean up
|
2023-06-12 20:21:55 -07:00 |
|
Harshini Srinath
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8487a82efd
|
Update csrsr.sv
Program clean up
|
2023-06-12 20:19:47 -07:00 |
|
Harshini Srinath
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32ba95a88f
|
Update csrsr.sv
Program clean up
|
2023-06-12 20:15:29 -07:00 |
|
Harshini Srinath
|
8c902a3ec2
|
Update csrs.sv
Program clean up
|
2023-06-12 19:53:41 -07:00 |
|
Harshini Srinath
|
5906b5e729
|
Update csrm.sv
Program clean up
|
2023-06-12 19:42:45 -07:00 |
|
Harshini Srinath
|
f7522ad53c
|
Update csri.sv
Program clean up
|
2023-06-12 19:32:04 -07:00 |
|
Harshini Srinath
|
7dc1595ccc
|
Update csrc.sv
Program clean up
|
2023-06-12 19:03:34 -07:00 |
|
Harshini Srinath
|
ba23a90e9d
|
Update csr.sv
Program clean up
|
2023-06-12 18:51:37 -07:00 |
|
David Harris
|
b15c5e2a51
|
Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
|
2023-06-09 14:40:01 -07:00 |
|
David Harris
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e2e6f6f255
|
Added named support for Zicntr and Zihpm
|
2023-06-09 09:35:51 -07:00 |
|
Ross Thompson
|
822e60bd3d
|
Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.
|
2023-06-05 15:42:05 -05:00 |
|
Ross Thompson
|
e56497101a
|
Updated source code to be compatible with verilator 5.011 for lint only.
|
2023-05-31 10:44:23 -05:00 |
|
Ross Thompson
|
923c00b928
|
I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types.
|
2023-05-26 13:56:51 -05:00 |
|
Ross Thompson
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d47951fb51
|
The privileged unit is parameterized using Lim's method.
|
2023-05-26 12:03:46 -05:00 |
|
Ross Thompson
|
81b33fb48e
|
Fixes load and store stall counters.
|
2023-05-22 10:08:49 -05:00 |
|
David Harris
|
e962e95e53
|
CSR code cleanup
|
2023-04-27 14:12:57 -07:00 |
|
David Harris
|
e69ebc45c0
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-04-27 07:30:07 -07:00 |
|
Alexa Wright
|
79031e3de0
|
Added better comment for the exclusion in privdec.sv
|
2023-04-26 16:25:55 -07:00 |
|
Alexa Wright
|
55a74fd315
|
Excluded and added coverage for WFI test case.
|
2023-04-25 17:06:57 -07:00 |
|
David Harris
|
03448aa691
|
Commented about Sstvecd trap vector alignment
|
2023-04-24 12:20:33 -07:00 |
|
Diego Herrera Vicioso
|
c681789296
|
Excluded coverage for impossible cases in wficountreg and status.MPRV
|
2023-04-24 02:06:53 -07:00 |
|
David Harris
|
1d532dfcfc
|
Fault on writes to odd-numbered PMPCFG in RV64
|
2023-04-22 15:32:39 -07:00 |
|
Diego Herrera Vicioso
|
34dd481f93
|
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
|
2023-04-15 23:13:39 -07:00 |
|
Limnanthes Serafini
|
c427b4c896
|
Misc typo and indent fixing.
|
2023-04-13 16:54:15 -07:00 |
|
Alexa Wright
|
34fd402f23
|
Excluded coverage for misaligned instructions
|
2023-04-10 23:18:25 -07:00 |
|
David Harris
|
7ad8d7f774
|
Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed
|
2023-04-07 20:43:28 -07:00 |
|
Ross Thompson
|
d1ac175e27
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2023-04-05 14:55:12 -05:00 |
|
Ross Thompson
|
7c2512446c
|
Progress on bug 203.
|
2023-04-05 13:20:04 -05:00 |
|
David Harris
|
b7b1f2443f
|
Fixed WFI to commit when an interrupt occurs
|
2023-04-04 09:32:26 -07:00 |
|
David Harris
|
b95730e3a1
|
Coverage improvements in ieu, hazard units
|
2023-03-31 08:33:46 -07:00 |
|
David Harris
|
77d5f1c81b
|
Refactored InstrValidNotFlushed into CSR Write signals
|
2023-03-30 17:06:09 -07:00 |
|