15 Commits

Author	SHA1	Message	Date
Harshini Srinath	01fc7c5284	Fixed formatting	2023-07-30 18:36:25 -07:00
Harshini Srinath	811e2fd94c	Fixed formatting	2023-07-30 18:30:23 -07:00
Harshini Srinath	01bbddc5da	Fixed formatting	2023-07-30 18:27:22 -07:00
Harshini Srinath	a697c89a2a	Fixed formatting	2023-07-30 18:18:24 -07:00
Harshini Srinath	1bc1a68210	Fixed formatting	2023-07-30 18:06:25 -07:00
Harshini Srinath	86164acc84	Fixed formatting	2023-07-30 18:00:39 -07:00
Harshini Srinath	6b5aa47f23	Fixed formatting	2023-07-30 17:54:47 -07:00
Harshini Srinath	8c7ea5a47a	Fixed formatting	2023-07-30 17:46:23 -07:00
Harshini Srinath	69711503a8	Fixed formatting	2023-07-30 17:39:37 -07:00
Harshini Srinath	70599d3153	Fixed formatting	2023-07-30 17:38:22 -07:00
David Harris	a192214f86	Fixed lint errors, presumably detected by latest version of verilator	2023-06-11 06:48:42 -07:00
Ross Thompson	340aac0934	Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.	2023-05-26 16:00:14 -05:00
Ross Thompson	e6d25b7f70	Finished fpu parameterization using Lim's method.	2023-05-26 14:40:06 -05:00
Mason Adams	4468086e06	Removed redundent expression to increase coverage	2023-04-17 14:13:26 -05:00
David Harris	99d179dd3e	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00