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2176 Commits

Author SHA1 Message Date
Kip Macsai-Goren
fc549d1595 Merge remote-tracking branch 'upstream/main' into main 2023-02-03 09:31:06 -08:00
Kevin Kim
3d67e48bef Merge branch 'main' of https://github.com/kipmacsaigoren/cvw 2023-02-03 16:00:36 +00:00
Kevin Kim
d47a44a62f ALU changes (ZBB) 
- handles inverted operand instructions
- handles shift-and-add instructions
 2023-02-03 16:00:32 +00:00
Ross Thompson
4547da80ea Fixed bug #49. 
FFLAGS was updated while the pipeline was stalled.
Also I found serveral performance counters which had similar issues.
 2023-02-03 00:39:26 -06:00
Ross Thompson
659b511616 Lee Moore found another bug using imperas. 
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
 2023-02-02 23:52:21 -06:00
Kevin Kim
a0adcf6a85 Merge branch 'openhwgroup:main' into main 2023-02-02 21:41:55 -08:00
Kevin Kim
f0730c13e2 Started Zbb 
-Performs byte instructions (orc.b, rev8 (32/64))
 2023-02-03 05:40:38 +00:00
Kevin Kim
a0ea436b9c zbs minor lint fix 2023-02-03 05:31:50 +00:00
Kevin Kim
44e5a7e913 zbc initial done; passes lint. 
clmul logic changes have not verified yet
 2023-02-03 04:48:23 +00:00
Kevin Kim
adc96ecaaa added bit reverse module, passes lint 2023-02-02 23:10:57 +00:00
Kevin Kim
e2228f6341 started zbc 2023-02-02 20:11:11 +00:00
Kevin Kim
aadc1de746 zbs passes lint 2023-02-02 20:04:38 +00:00
James Stine
924e55325c Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22 2023-02-02 13:54:25 -06:00
Kevin Kim
ae5d7844a9 clmul finished initial hdl; passes lint 2023-02-02 19:49:14 +00:00
James Stine
9a5023a17e Modify generic/mem for rv32gc ram2 2023-02-02 13:28:18 -06:00
Kevin Kim
f07ffbb63b continued clmul unit 2023-02-02 18:54:33 +00:00
Kevin Kim
bd8f0189ee started clmul 2023-02-02 16:40:58 +00:00
Ross Thompson
3838ab232b Fixed bug #47 discovered by Lee Moore. 
ECALL and EBREAK do not commit their results.
 2023-02-02 08:52:06 -06:00
Ross Thompson
7f207527ce Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-02-02 08:48:19 -06:00
Kip Macsai-Goren
0281330fe8 Merge remote-tracking branch 'upstream/main' into main 2023-02-01 21:31:57 -08:00
Kip Macsai-Goren
f126d1e0ef added beginning of a ZBS instruction module to the ALU. Control signals still needed 2023-02-01 21:31:25 -08:00
James Stine
fc5692629a Update ram2 and other memories and associated wrappers 2023-02-01 17:03:48 -06:00
Ross Thompson
3276353b8c Minor branch predictor bug fix. 2023-02-01 10:59:38 -06:00
Ross Thompson
51a2a71410 Removed unused signal. 2023-02-01 10:27:58 -06:00
David Harris
ce82d8d550 Fixed merge conflict to get synthesis working again 2023-02-01 04:43:57 -08:00
Ross Thompson
6fb624950e Minor change to btb. 2023-02-01 00:24:54 -06:00
Madeleine Masser-Frye
57b35c293d added memories (not tested) 2023-02-01 06:08:27 +00:00
Ross Thompson
d5c1ac4e11 Minor optimization to btb. 2023-01-31 22:03:51 -06:00
David Harris
5d7dcfb748 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-31 14:40:19 -08:00
Ross Thompson
7166fcd4d2 Updates to RAS. 2023-01-31 15:17:32 -06:00
Ross Thompson
dd556e8763 Simplified RAS. 2023-01-31 14:54:05 -06:00
Ross Thompson
122809b2b2 RAS file name was spelled wrong. 2023-01-31 14:35:05 -06:00
Ross Thompson
bfbf534830 Created scripts to install imperas and run a single test using imperas. 2023-01-31 13:51:05 -06:00
Ross Thompson
eededd1ba9 Fixed remaining bugs in the imperas merge. 2023-01-31 13:04:26 -06:00
Ross Thompson
0678e70b4b Merge branch 'imperas' 2023-01-31 12:46:22 -06:00
Ross Thompson
52bdf32575 Minor bug fix in gshare. 2023-01-31 10:45:32 -06:00
Ross Thompson
e7b91d5934 Renamed signals in RAS. 2023-01-31 10:44:11 -06:00
Ross Thompson
b4854d8e94 Found small bug in gshare. 2023-01-31 00:17:49 -06:00
Ross Thompson
20e99dce73 Fixed parameterization in testbench. 2023-01-31 00:11:01 -06:00
Ross Thompson
b64b3016e2 Parameterized testbench branch predictor preload. 2023-01-31 00:08:11 -06:00
Ross Thompson
22ef051603 More branch predictor cleanup. 2023-01-30 23:55:52 -06:00
Ross Thompson
61759af9dc Improved signal names. 2023-01-30 23:51:04 -06:00
Ross Thompson
165b4858d7 Major cleanup of branch predictor. 2023-01-30 23:37:34 -06:00
Ross Thompson
57ab5a7488 Simplified gshare. 2023-01-30 19:27:18 -06:00
Ross Thompson
0e29a5f9c2 Minor gshare optimization. 2023-01-30 18:13:12 -06:00
David Harris
6777fd9b55 Restored top-level modules without import statements 2023-01-30 12:54:40 -08:00
David Harris
49e45f45b7 Moved out version of wally using package because synthesis isn't working yet 2023-01-30 12:48:52 -08:00
David Harris
1e7c9f026c Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-30 11:00:51 -08:00
Ross Thompson
7a4218788c Imperas found a real bug in virtual memory. 
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.

Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
 2023-01-30 11:47:51 -06:00
Ross Thompson
63267ff378 optimized branch predictor by removing unnecessary registers. 2023-01-29 22:39:37 -06:00