Ross Thompson
fb234d506d
Formatted subword* and bytemask.
2023-01-18 18:20:22 -06:00
Ross Thompson
469efa61af
Formatting.
2023-01-18 18:17:48 -06:00
Ross Thompson
cbf46f417a
Formatting.
2023-01-18 18:16:56 -06:00
Ross Thompson
22eee73a45
Formatting.
2023-01-18 18:16:20 -06:00
Ross Thompson
2048edb7a0
Renamed signals in amoalu.
2023-01-18 18:13:18 -06:00
Ross Thompson
40c0e67930
Formatting.
2023-01-18 18:05:11 -06:00
Ross Thompson
2622f5dfb8
Formatting.
2023-01-18 17:56:47 -06:00
Ross Thompson
fc5424fa62
Formatting
2023-01-18 16:58:03 -06:00
Ross Thompson
c34acab1d7
Formating.
2023-01-18 16:47:40 -06:00
Ross Thompson
4b47598138
Moved amoalu to lsu.
2023-01-17 22:45:46 -06:00
Ross Thompson
f146a01344
Cleaned up ahbcacheinterface.
2023-01-17 22:13:56 -06:00
Ross Thompson
d6c80d937c
Formatting progress.
2023-01-17 22:10:31 -06:00
Ross Thompson
c75a164f46
Added comments to dtim and ahbcacheinterface.
2023-01-17 21:56:55 -06:00
David Harris
7f68a55b8c
Clean up tabs
2023-01-15 18:23:09 -08:00
David Harris
b613722617
trap comments
2023-01-13 19:44:38 -08:00
Ross Thompson
e0867b1840
Completed review of LSU.
2023-01-11 19:06:03 -06:00
Ross Thompson
318ceba34d
Improved LSU formating.
2023-01-11 18:52:46 -06:00
Ross Thompson
b60e9730a7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2023-01-11 17:15:49 -06:00
David Harris
8c6ddcc15b
changed name to CORE-V-WALLY
2023-01-11 15:15:08 -08:00
Ross Thompson
bccef3b39c
Updated header for LSU.
2023-01-11 17:15:07 -06:00
David Harris
3ea4dd4898
Changed Wally to CORE-V Wally
2023-01-11 14:03:44 -08:00
David Harris
739c2c8322
Changed MIT license to Solderpad License
2023-01-10 11:35:20 -08:00
David Harris
01525399cc
Removed unused signals; added check for atomic in pmachecker
2023-01-07 05:59:56 -08:00
Ross Thompson
a2de53aeeb
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
2cc4d66ded
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
David Harris
e74d47bcb4
Renamed renamed sram to ram
2022-12-20 08:36:45 -08:00
Ross Thompson
7d04675073
Cleanup comments.
2022-12-16 17:08:35 -06:00
Ross Thompson
ffc5bce0b6
Renamed CPUBusy in LSU.
2022-12-11 15:52:51 -06:00
Ross Thompson
c50a2bd8bf
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
3ddf509f28
Renamed CPUBusy to Stall in cache.
2022-12-11 15:49:34 -06:00
Ross Thompson
4aadd87679
Moved CPUBusy out of HPTW.
2022-12-11 15:48:00 -06:00
Ross Thompson
1e2180ef98
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
f03d5d3ac8
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
1a00e7bbee
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
a27b81ef90
Changed IMWriteDataM to IHWriteDataM.
2022-11-13 12:27:48 -06:00
Ross Thompson
90697ef888
Moved all remaining bus logic from the LSU into ahbcacheinterface.
2022-11-11 14:30:32 -06:00
Ross Thompson
64b818c49a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-10 15:46:25 -06:00
Ross Thompson
31d5eabd77
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
42c0a10d07
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
David Harris
9b20bf341e
Moved lsuvirtmem muxes into hptw
2022-11-07 11:13:34 -08:00
Ross Thompson
98d4929c57
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
Ross Thompson
270a83352f
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
54bd1fb806
Small cleanup of interlockfsm.
2022-10-22 16:29:51 -05:00
Ross Thompson
e5cae3bfa0
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
5ad3ee6b54
Broken don't use this state.
2022-10-19 14:31:22 -05:00
Ross Thompson
de1e569ee9
Noted possible bug with endianness during hptw.
...
Minor complexity reduction in interlockfsm. I think there is a lot of room to simplify.
2022-10-19 12:20:19 -05:00
Ross Thompson
2c80c2b35f
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
Ross Thompson
47915421c2
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
fccaad7f3f
Fixed LSU to correctly handle the difference between LLEN and AHBW.
2022-10-12 12:06:15 -05:00
Ross Thompson
12a6a9f83b
Actually fixed the bus width issue coming out of the cache.
...
The root cause is the ahb bus width can be different from LLEN.
If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well.
Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.
2022-10-12 11:33:10 -05:00
