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Author SHA1 Message Date
Jordan Carlin
36579d5aec Fix git_check return values 2024-07-19 11:09:27 -07:00
Jordan Carlin
af796116c9 Refactor git repo checks to use a function 2024-07-19 11:09:27 -07:00
Jacob Pease
6018ab82ab Added tentative spi_send_byte function. 2024-07-19 12:30:32 -05:00
Jordan Carlin
85a84dcbed Update setup scripts to be more verbose about errors 2024-07-19 10:14:19 -07:00
Jordan Carlin
6e5554f429 Add additional packages 2024-07-19 10:14:19 -07:00
Jacob Pease
5123a43ba2 Added initial spi code to fpga/zsbl 2024-07-19 11:35:12 -05:00
Rose Thompson
6aaa77dae0 Merge pull request #887 from davidharrishmc/dev 
Fully decode decompressed instructions, including hints and illegal registers/immediates
 2024-07-19 09:23:36 -05:00
David Harris
12c8449275 Detect illegal compressed immediates, hints 2024-07-18 22:48:32 -07:00
David Harris
bd1658754f Neatly formatted decompress.sv 2024-07-18 22:01:43 -07:00
David Harris
a4e84d6f15 Modified decompressor to look for illegal x0 values and hints 2024-07-18 21:38:17 -07:00
Jordan Carlin
5661dc4a03 Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-07-18 21:36:00 -07:00
Rose Thompson
79d0cb96c2 Added verilog-ethernet as a submodule. Hoping we can make use of sparse-checkout as there are so many files in this repo. 2024-07-18 18:22:26 -05:00
David Harris
1637f4f1e3 Check legal compressed nonzero destination registers, add c.nop decoding 2024-07-18 09:30:16 -07:00
David Harris
566583639d Refactored decompression to use simpler default illegal instruction 2024-07-18 08:26:58 -07:00
Rose Thompson
3d8adabe34 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-18 09:38:20 -05:00
David Harris
464b6ff72f Converted regression-wally to use argparse 2024-07-17 06:04:21 -07:00
Rose Thompson
46538e3dac Merge pull request #884 from davidharrishmc/dev 
Attempt on functional coverage
 2024-07-16 18:42:19 -05:00
Rose Thompson
f84aa40b13 Fixed wally.do to correctly log functional coverage. 2024-07-16 15:52:52 -05:00
David Harris
8f83ff1a94 Fixed slli.uw bug reported by Lee Moore 16 July 2024 2024-07-16 09:28:05 -07:00
David Harris
fa75077d2f More attempts at functional coverage 2024-07-15 15:34:44 -07:00
David Harris
2c487935e6 Attempt at functional coverage; breaks code and functional coverage 2024-07-15 14:20:48 -07:00
David Harris
2d7f6a969d Ignore functional coverage outputs 2024-07-15 14:19:37 -07:00
David Harris
2e0058c1ed Fixed .gitignore 2024-07-15 05:46:35 -07:00
David Harris
2fd8d436d4 Ignoring more sim files 2024-07-15 05:34:50 -07:00
David Harris
04cd2c8ea4 Renamed --coverage to --ccov and moved UCDB files to questa/ucdb 2024-07-15 05:32:16 -07:00
David Harris
29bd6a30ab Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-07-15 04:27:59 -07:00
David Harris
affe15191e Fixed wsim running iterelf tests/coverage 2024-07-15 03:44:14 -07:00
David Harris
459eaaef6a Initial effort to make testbench_fp compatible with Verilator without breaking Questa 2024-07-14 20:08:33 -07:00
David Harris
1b5e63ebe2 Fixed elf handling 2024-07-14 09:49:15 -07:00
Rose Thompson
c53ea43ef9 Merge pull request #880 from davidharrishmc/dev 
wsim elf handling and RV64GCK lockstep support
 2024-07-14 11:40:30 -05:00
David Harris
779458f14a Waive CBO failures in iterelf because ImperasDV does not handle them properly yet 2024-07-13 22:08:57 -07:00
David Harris
904a081218 allow wsim to take .elf in testsuite argument; print error if ELF not found 2024-07-13 21:59:26 -07:00
David Harris
26d4fbcc19 Switched ImperasDV to RV64GCK model to support crypto (issue #872) 2024-07-13 21:42:14 -07:00
Rose Thompson
35a3d2e43a Merge pull request #879 from JacobPease/main 
main
 2024-07-12 09:32:13 -05:00
Jacob Pease
7f72fb8583 Updated riscv,isa-extensions property with the correct syntax. Added riscv,cbom-block-size. 2024-07-12 09:28:54 -05:00
Jordan Carlin
a4967138b6
Merge pull request #875 from ross144/main 2024-07-11 18:05:14 -07:00
Rose Thompson
82bd9ca200 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-11 11:32:12 -05:00
Rose Thompson
8f52e4ae42
Merge pull request #878 from JacobPease/main 
Commented out riscv,isa-extensions from Arty device tree until Linux kernel is updated.
 2024-07-11 11:25:24 -05:00
Jacob Pease
1a2607c3d9 Commented out riscv,isa-extensions from Arty device tree until Linux kernel is updated. 2024-07-11 10:53:18 -05:00
Ross Thompson
c72f0fd504 Added csr comparison. 2024-07-11 10:49:06 -05:00
Ross Thompson
abf9da01ab code cleanup. 2024-07-11 10:41:34 -05:00
Ross Thompson
f0096f5a43 Yay. It's actually working! The FPGA/ImperasDV hybrid is working. 2024-07-10 15:10:37 -05:00
Ross Thompson
e6dc962d11 Yay! the trigger is correctly working now! 2024-07-10 12:05:10 -05:00
Ross Thompson
cf986b5fb8 Really close to having the trigger in module work. 
Can trigger on the data of the correct frame, but trigger in is still not
working.
 2024-07-09 19:04:51 -05:00
Ross Thompson
6734685333 Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit. 2024-07-09 19:04:18 -05:00
Ross Thompson
e0a1f0e39f Really close now. 2024-07-09 14:21:43 -05:00
Ross Thompson
e488ee7225 Correctly sending the ethernet frame on a mismatch. Now just need to get vivado to actually trigger. 2024-07-09 14:16:13 -05:00
Ross Thompson
fd170a6583 Getting closer. 2024-07-09 14:09:56 -05:00
Ross Thompson
bf69a2e1cd Updated to use the newest imperasDV. 2024-07-09 12:30:18 -05:00
Rose Thompson
f83e6cf771 Fixed issue #874. 2024-07-08 14:48:52 -05:00