David Harris
1c1d3eb956
HPTW coverage improvements
2024-01-26 10:46:38 -08:00
David Harris
d2f645819d
Added override to fix issue 582 menvcfg.FIOM writability; restored PMA for uncore RAM affecting AMO operations
2024-01-24 06:46:14 -08:00
David Harris
66a1edb261
More coverage touchup
2024-01-23 23:11:49 -08:00
David Harris
7215f48dda
coverage improvements: fixing problems running ImperasDV on coverage tests
2024-01-23 22:21:01 -08:00
Jordan Carlin
0c13e14bbf
coverage improvements for mret when mpp = 3; update imperas config
2024-01-22 09:52:58 -08:00
David Harris
9260d3c424
Add Zfh support to imperas.ic, use Zicond in riscof now that it is fixed in riscv-arch-test
2024-01-18 22:46:07 -08:00
David Harris
9eb6d9c8b8
Added Zicond support
2024-01-11 07:37:15 -08:00
David Harris
c1ad6602a3
Added commented out B extension MISA to imperas.ic; not yet working
2023-12-21 11:04:41 -08:00
David Harris
4186b604e0
Updated imperas.ic to throw misalignment faults on uncachable memory regions
2023-12-19 12:53:21 -08:00
David Harris
29f57958a9
Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match
2023-12-14 15:32:36 -08:00
David Harris
68d49c37db
Changed PMA settings in imperas.ic so that peripherals require aligned accesses. This fixes WALLY-trap in ImperasDV.
2023-12-13 20:49:26 -08:00
David Harris
166c98b6f6
Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn
2023-12-13 19:43:17 -08:00
David Harris
6c017141c5
Renamed HADE to ADUE for Svadu
2023-12-13 11:49:04 -08:00
David Harris
d1bb5c7512
Imperas fix for satp modes supported
2023-11-21 21:52:11 -08:00
Rose Thompson
e5b7301ffe
Updated imperad dv vendor id and architecture id config.
2023-11-21 15:14:17 -06:00
Rose Thompson
b137759b45
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-11-20 10:34:36 -06:00
Rose Thompson
3594c08d4b
Modified linux imperas tests to
...
1. enable zicclsm
2. enable logging at 7000 ms
2023-11-20 10:30:35 -06:00
David Harris
cfaeeae25a
Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter
2023-11-15 08:15:01 -08:00
David Harris
426aabbc1a
Imperas commenting
2023-11-10 08:26:32 -08:00
David Harris
7e00581187
Add Svadu support and SPI to imperas configuration
2023-11-10 06:27:25 -08:00
David Harris
625652b9ca
Reporting stall path in synthesis script, support Zcb in Imperas
2023-11-09 06:59:29 -08:00
David Harris
2b183020d5
Fixed bit manpulation on imperas config
2023-11-06 14:11:01 -08:00
David Harris
9c4a7866b8
Fixed Svnapot_page_mask for imperas.ic
2023-11-05 06:51:01 -08:00
David Harris
434d6b2c5c
minfo test working again with mconfigptr for RV64
2023-10-15 06:41:52 -07:00
eroom1966
381cfdcb4b
bring upto date with latest IDV
2023-09-21 11:29:31 +01:00
eroom1966
5f358d1af7
add changes for latest IDV file layout
2023-06-16 16:43:53 +01:00
David Harris
004aeda362
Revert "Update for new layout of ImperasDV files"
2023-06-13 04:17:56 -07:00
eroom1966
d61ed17730
Update for new layout of ImperasDV files
2023-06-12 09:29:07 +01:00
David Harris
a34867d14e
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic. ImperasDV is happy with these privileged tests now
2023-04-10 07:05:06 -07:00
eroom1966
dc79710724
add support into configuration for Zb(a,b,c,s)
2023-04-06 16:30:14 +01:00
eroom1966
adafc8037d
add support for Sstc
2023-04-04 17:20:00 +01:00
David Harris
a6117e9bef
Updated imperas.ic to enable B extension
2023-04-03 17:55:30 -07:00
David Harris
c1ec1cb09c
Added SSTC support to imperas.ic and wallyTracer. Fixes many of the privileged tests
2023-03-31 10:54:03 -07:00
David Harris
60a8a26f2e
regression cleanup; unable to run buildroot coverage because of different config file
2023-03-31 09:59:38 -07:00
eroom1966
1a10e48ecf
update to allow running of ImperasDV with linux boot
...
optimize performance of the tracer
2023-03-27 09:46:16 +01:00
eroom1966
259fbc8d77
support linux
2023-03-22 17:10:32 +00:00
eroom1966
9ddfe52c9f
Fix MISA RO and UART addresses
...
It appears on inspection that the MISA register is read only in Wally
In which case this has now also been set in the ImperasDV representation
Also the Addresss for the UART R/W privileges are corrected
2023-03-13 11:07:19 +00:00
eroom1966
0233130d9c
Enhancements to support the PMA ranges
2023-03-10 14:09:22 +00:00
eroom1966
39ac3cd18f
Add support for setting PMP registers
...
Add support for async DV
2023-03-08 12:44:53 +00:00
eroom1966
fe4d9d3e37
fix the memory map privileges in the REF model view
2023-03-02 15:25:27 +00:00
eroom1966
f86a12f282
update testbench for memory privileges
...
also update configuration to define value of mimpid
2023-03-01 15:37:11 +00:00
eroom1966
237a115377
add files to support coverage
2023-02-15 11:13:50 +00:00
Ross Thompson
70e96a7531
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-06 16:35:20 -06:00
eroom1966
d88b56eebc
remove leading space
2023-02-06 14:01:05 +00:00
eroom1966
232bfbcfd0
remerge changes
2023-02-06 13:43:12 +00:00
Ross Thompson
4fed1d5e3d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-04 11:28:26 -06:00
David Harris
80f42a8638
Renamed regression to sim
2023-02-02 14:48:23 -08:00
