James E. Stine
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48c1e19247
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Add bestSynths.csv that are the initial values. If this is re-run after ppaAnalysis.py is run, more refinement can be made
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2023-11-10 21:06:24 -06:00 |
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James E. Stine
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26db31cfde
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update README for ppaSynth.py
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2023-11-10 21:05:42 -06:00 |
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David Harris
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35efb7082c
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fdivsqrt parameter cleanup
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2023-11-10 18:33:08 -08:00 |
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David Harris
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6ed5ba4a85
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Simplified out LOGRK parameter
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2023-11-10 18:19:41 -08:00 |
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David Harris
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1302a89baf
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divider cleanup
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2023-11-10 18:01:13 -08:00 |
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David Harris
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d92f3e0216
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fdivsqrt cleanup
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2023-11-10 16:42:32 -08:00 |
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David Harris
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fbd6fce1ce
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-10 16:40:54 -08:00 |
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Rose Thompson
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534538b216
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Simplification.
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2023-11-10 18:39:36 -06:00 |
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Rose Thompson
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7158aa8390
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Yay! Zicclsm passes my regression test now.
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2023-11-10 18:28:51 -06:00 |
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Rose Thompson
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c29ef1666b
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Found another bug in the RTL's Zicclsm alignment.
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2023-11-10 18:26:55 -06:00 |
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Rose Thompson
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fa6e53d8cf
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Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
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2023-11-10 17:58:42 -06:00 |
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Rose Thompson
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2491ef0e23
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Fixed some more bugs in the Zicclsm signature.
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2023-11-10 17:36:10 -06:00 |
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Rose Thompson
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3245e2a99e
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Fixed bug in the Zicclsm test.
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2023-11-10 17:34:23 -06:00 |
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Rose Thompson
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bd9a750583
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Fixed spill bugs in the aligner.
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2023-11-10 17:18:45 -06:00 |
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Rose Thompson
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b555620ac8
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Fixed bug in the misaligned access test.
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2023-11-10 17:02:15 -06:00 |
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David Harris
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f539f6171b
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Simplified integer postnormalization shift
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2023-11-10 14:55:36 -08:00 |
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David Harris
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72ad1d361c
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Simplified IntDivNormShift
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2023-11-10 14:28:57 -08:00 |
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Rose Thompson
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4b24878053
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Merge branch 'main' into Zicclsm
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2023-11-10 16:15:32 -06:00 |
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Rose Thompson
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329f4456b0
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Missed tests.vh.
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2023-11-10 16:10:10 -06:00 |
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Rose Thompson
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89bf1a5cf9
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Fixed bug which broke the non Zicclsm configs.
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2023-11-10 16:08:04 -06:00 |
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David Harris
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b8bdb1c7d1
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Simplified cycle count logic
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2023-11-10 14:00:27 -08:00 |
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David Harris
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083ed09f1e
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Reduced duplicated logic in fdivsqrtcycles
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2023-11-10 11:25:54 -08:00 |
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David Harris
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4d77f28a19
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Divsqrt cleanup: change Q to U, commenting code
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2023-11-10 11:21:02 -08:00 |
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David Harris
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a1f94c9b0c
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fdivsqrt parameter cleanup
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2023-11-10 09:11:15 -08:00 |
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Rose Thompson
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5026772301
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Merge pull request #463 from davidharrishmc/dev
Dev
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2023-11-10 08:48:07 -08:00 |
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David Harris
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fedf9c8a5a
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Started cleaning up shifting leading 1 in fdivsqrt
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2023-11-10 08:46:55 -08:00 |
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David Harris
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68115c6d6b
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Imperas commenting
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2023-11-10 08:26:32 -08:00 |
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David Harris
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ae769e90aa
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Add Svadu support and SPI to imperas configuration
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2023-11-10 06:27:25 -08:00 |
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David Harris
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5dbe869339
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Merge pull request #460 from naichewa/main
removed vestigial logic, added comments, deleted unused signals
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2023-11-10 05:18:57 -08:00 |
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naichewa
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fd06472de8
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Cleanup
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2023-11-09 16:52:55 -08:00 |
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naichewa
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2b4cf01a21
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Remove old 2/4 bit logic, add comments,
clean up unused signals
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2023-11-09 16:48:11 -08:00 |
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David Harris
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1876d5bebf
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-09 10:33:25 -08:00 |
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Rose Thompson
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89a303fbef
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Merge pull request #458 from stineje/main
fix to setup.csh and also ppaSynth.py
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2023-11-09 10:20:05 -08:00 |
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David Harris
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d1e73ee9c2
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Reporting stall path in synthesis script, support Zcb in Imperas
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2023-11-09 06:59:29 -08:00 |
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James E. Stine
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29d6fe8fea
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update README on ppa
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2023-11-09 01:00:33 -06:00 |
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James E. Stine
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20e1e12234
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update ppaSynth.py with runCommand
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2023-11-09 00:52:40 -06:00 |
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James E. Stine
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5361766045
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Add encoding for utf-8 on wrapperGen.py to avoid issue with incorrect encoding on RHEL C-shell
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2023-11-08 23:57:59 -06:00 |
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David Harris
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917af1e988
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-08 16:06:50 -08:00 |
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David Harris
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01d24b3505
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Merge pull request #459 from naichewa/main
hardware interlock and hold mode fixes
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2023-11-08 16:06:39 -08:00 |
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naichewa
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997318d7f9
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updated to-do comments
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2023-11-08 15:28:51 -08:00 |
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naichewa
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7d88050ecd
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fix hardware interlock, hold mode deassert
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2023-11-08 15:20:51 -08:00 |
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James E. Stine
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30c230ba95
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Update to ppaSynth and ppaAnalyze - still have to push in mod for ppaAnalyze to plot more refined plots as well as some other plots - I have a fix working - just need to push in which will do later today
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2023-11-08 14:00:36 -06:00 |
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James E. Stine
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825386241a
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add typo on setting WALLY for C-shell that caused some incompatability issues
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2023-11-08 13:59:04 -06:00 |
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Rose Thompson
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34d521a9ba
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Merge pull request #455 from davidharrishmc/dev
Bit manipulation imperas config, fsqrt code changes to match chapter
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2023-11-08 08:27:15 -08:00 |
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David Harris
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e7bb50c81e
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-08 02:55:00 -08:00 |
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David Harris
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f3e9c32fb4
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Merge pull request #456 from naichewa/main
fifo fixes and edge case testing
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2023-11-08 02:54:06 -08:00 |
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naichewa
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fbeaad4150
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fifo fixes and edge case testing
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2023-11-07 17:59:46 -08:00 |
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David Harris
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1bac0de954
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Reparitioned sign logic in fdivsqrt to match paper
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2023-11-06 14:11:42 -08:00 |
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David Harris
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fac0c1b125
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Fixed bit manpulation on imperas config
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2023-11-06 14:11:01 -08:00 |
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Rose Thompson
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b0652db5d4
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Merge pull request #453 from davidharrishmc/dev
Fixed regression error of watchdog timeout when PCM is optimized out of the IFU
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2023-11-05 15:53:57 -08:00 |
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