Rose Thompson
f7b00c7af9
Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests.
2023-10-30 14:54:58 -05:00
Rose Thompson
560a843cea
Finally lints cleanly.
2023-10-30 14:00:49 -05:00
Rose Thompson
610969726e
Progress.
2023-10-27 16:31:22 -05:00
Rose Thompson
b2c61737bf
Passes lint with some exceptions. Still need to add misaligned store support.
2023-10-27 14:41:42 -05:00
Rose Thompson
42b2dad6ad
At least have the aligner integrated, but not tested.
2023-10-27 13:55:16 -05:00
Rose Thompson
ff85832454
Addec ZICCLSM to config files and started on lsu instance.
2023-10-27 13:07:23 -05:00
Rose Thompson
d648e199e1
The misaligned load alignment lints.
2023-10-27 11:41:49 -05:00
Rose Thompson
839ff28d32
Added file.
2023-10-27 09:49:44 -05:00
Rose Thompson
e7edd0084e
Progress on misaligned load/stores.
2023-10-27 09:35:44 -05:00
Rose Thompson
00851dab2a
begin implemenation of Zicclsm.
2023-10-26 11:51:20 -05:00
Rose Thompson
dd9059317f
Cleaned up the implementation changes for wfi.
2023-10-24 23:11:48 -05:00
Rose Thompson
e4aebbaaa5
This version passes the regression test and solves issue #200 . wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps.
2023-10-24 22:58:26 -05:00
Rose Thompson
bc877e9ca7
Possible fix for wfi.
2023-10-24 18:08:33 -05:00
Rose Thompson
bce15ce367
Added support for branch counters when there is no branch predictor.
2023-10-23 15:32:03 -05:00
Rose Thompson
2b031ea445
Fixed issue 250. instruction classification was not correct for jalr ra (non zero).
2023-10-23 15:30:43 -05:00
David Harris
aa3bc10259
Modified log2 coding to avoid synthesis warning
2023-10-19 11:16:02 -07:00
David Harris
09b3a49471
Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates
2023-10-18 05:50:41 -07:00
David Harris
b39ba7b4f8
Renamed wally-config to config in many comments
2023-10-16 13:49:09 -07:00
David Harris
b8a17afd5d
minfo test working again with mconfigptr for RV64
2023-10-15 06:41:52 -07:00
Ross Thompson
4a61d1b4f1
Fixed issue #412
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The root cause was DTLB miss leads to page fault exception with concurrent I$ miss. The HPTW hits all entries in the D$ and quickly faults. However the I$ is still waiting on the main memory.
The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.
The simplest solution is to use CommittedF to delay Exceptions like with Interrupts. Note this cannot happen with CommittedM. If the ITLB misses and the D$ also need to fetch a from the bus an ITLB page fault exception will not trigger the trap until a few stages later.
2023-10-09 16:03:37 -05:00
David Harris
d80cb36778
Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there
2023-10-04 12:28:12 -07:00
David Harris
42157eaf94
UpdateDA cleanup: don't assert UpdateDA when there is no SVADU
2023-10-04 09:57:13 -07:00
David Harris
df7f2679d7
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
Ross Thompson
1a003019d6
Actually fixed non-power of 2 issue with RAS.
...
Added RAS swapping to branch predictor scripts and configurations.
2023-09-27 12:25:05 -05:00
Ross Thompson
9ec2bfd052
Fixed sutble RAS bug when the stack size was not a power of 2.
2023-09-27 12:00:47 -05:00
Ross Thompson
a910425adf
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-09-14 10:16:54 -05:00
Ross Thompson
7c89154a7f
Slight modification to cachefsm.
2023-09-05 14:07:58 -05:00
Ross Thompson
f00df8d121
Merge pull request #407 from davidharrishmc/dev
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initial spill logic improvement
2023-09-05 13:29:37 -05:00
Ross Thompson
e39fc44efd
Merge pull request #406 from magpyed/cachesim_fix
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Properly gate LRUWriteEn with ~FlushStage
2023-09-05 11:10:58 -05:00
David Harris
6ab71ffca6
initial spill logic improvement
2023-09-03 04:21:13 -07:00
David Harris
1ced158596
tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
2023-09-02 12:56:36 -07:00
Limnanthes Serafini
b334e4ff1f
Properly gate LRUWriteEn with ~FlushStage
2023-09-01 23:31:02 -07:00
David Harris
98fa3a78dd
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
Kevin Kim
e4ed61a2ce
Merge branch 'openhwgroup:main' into synth_wrapper_gen
2023-08-28 09:03:10 -07:00
Kevin Kim
fc25afb3cb
make synth integerates wrapper generation and runs synth on wrapper
2023-08-28 09:02:56 -07:00
Ross Thompson
e7becd53d7
Merge pull request #398 from davidharrishmc/dev
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Completed basic tests of svnapot and svpbmt
2023-08-28 09:10:20 -05:00
David Harris
10549b7787
Completed basic tests of svnapot and svpbmt
2023-08-28 06:57:35 -07:00
Kevin Kim
9217e1e767
synth works
2023-08-26 21:11:21 -07:00
David Harris
75986d6641
Fixed merge conflict for ZICBOP
2023-08-25 18:41:57 -07:00
David Harris
3721f8347d
Preparing to merge with CBO* changes
2023-08-25 18:41:03 -07:00
David Harris
c07ad03f9d
Initial implementation of SVNAPOT and SVPBMT does not break regression
2023-08-25 18:33:08 -07:00
David Harris
9f44241d0f
Added N and PBMT bits to MMU PTE
2023-08-24 19:44:46 -07:00
David Harris
847c0dd099
Merge pull request #393 from ross144/main
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Implemented and tested CBOZ instruction
2023-08-24 19:17:38 -07:00
David Harris
d12be1faac
Merge pull request #394 from harshinisrinath1001/main
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Improved testing of csri with priv.S!
2023-08-24 19:16:50 -07:00
harshinisrinath
49014e61bc
Improved testing of csri with priv.S
2023-08-24 18:39:15 -07:00
Ross Thompson
284ff0ab0b
Fixed minor performance bug with CBOZ.
2023-08-24 17:08:20 -05:00
Ross Thompson
fbcf6be06d
Now have CBOZ instructions working!
2023-08-24 16:47:35 -05:00
David Harris
aad722ffb1
Check for legal SATP mode values
2023-08-24 05:18:04 -07:00
Ross Thompson
e8bc339638
Oups there was a bug in the SATP fix. RV32GC was broken by the changes.
2023-08-23 09:42:46 -05:00
Ross Thompson
d9a001e87a
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-08-23 09:15:13 -05:00
