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Author SHA1 Message Date
Katherine Parry
90eb4fc1f1 minor optimizations and renaming 2022-12-29 15:54:17 -06:00
Katherine Parry
89e8df084a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-29 12:37:51 -06:00
David Harris
776f4714af Clean up names and comments in divsqrt 2022-12-29 08:02:44 -08:00
David Harris
6664cb9db4 Factored out hardware unique to RV64 and to IDIV 2022-12-29 07:36:26 -08:00
Katherine Parry
1b4fa38510 one bitt removed from inital lignment shift 2022-12-28 17:46:53 -06:00
Alessandro Maiuolo
7c19665dea added script in pipelined folder to run regressions with all radix/copies configurations 2022-12-28 07:32:35 -08:00
David Harris
7780b44973 fdivsqrtfsm conditional on IDIV (fixed typo) 2022-12-27 22:16:48 -08:00
David Harris
5ee44b7405 fdivsqrtfsm conditional on IDIV 2022-12-27 22:15:45 -08:00
David Harris
db933aa7e2 fdivsqrtfsm conditional on IDIV 2022-12-27 22:14:09 -08:00
Cedar Turek
ef360f0539 idiv passing radix 2, four copies 2022-12-27 22:11:18 -08:00
Cedar Turek
4ed2c6255c idiv passing radix 2, four copies 2022-12-27 22:10:48 -08:00
David Harris
9964fc9ebe Moved IDIV in fdivsqrtfms into generate block 2022-12-27 22:04:50 -08:00
David Harris
a832605658 Moved IDIV for postproc into generate block 2022-12-27 22:02:14 -08:00
David Harris
d59878a886 Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc 2022-12-27 21:53:00 -08:00
Cedar Turek
a559abe554 Fixed cycles for multiple iterations. 2-copies radix 2 passing regression. 2022-12-27 21:34:27 -08:00
David Harris
665b545fd0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-27 21:30:13 -08:00
David Harris
87abed6722 cleanup 2022-12-27 21:29:36 -08:00
David Harris
6cf73cdaee Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M 2022-12-27 21:24:38 -08:00
David Harris
c08811357c Renamed muldiv to mdu 2022-12-27 19:57:10 -08:00
Ross Thompson
a129e27502 signal name changes in ram2p. 2022-12-27 15:07:01 -06:00
Ross Thompson
66b2fbd836 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-27 15:06:25 -06:00
Ross Thompson
3f4b3a4159 Added about moving decompressed config generate. 2022-12-27 15:04:55 -06:00
David Harris
dfc0b5d1ad Removed MDUE from unnecessary places in fdivsqrt 2022-12-27 10:42:40 -08:00
David Harris
4850d058b2 fdiv typo 2022-12-27 10:30:42 -08:00
David Harris
acc9498ae2 Made SqrtE only true on square root so gating with ~MDUE can be removed) 2022-12-27 10:27:07 -08:00
David Harris
e34b8139af Check for non-negative W in int sign handling 2022-12-27 06:35:17 -08:00
Cedar Turek
f48b7d7ef9 fpu idiv working on all configs with 1 copy of radix 2! 2022-12-26 23:18:28 -08:00
Cedar Turek
0b14aa852d fpu passing idiv tests on rv32gc 1 copy of radix 2! 2022-12-26 21:47:56 -08:00
Cedar Turek
bebaf08bed took out otfc swap. updated postprocessing quotient/remainder logic for int div. 2022-12-26 21:03:56 -08:00
David Harris
c326a274ac Fixed early termination for square root 2022-12-26 08:54:57 -08:00
David Harris
2de66e9eef Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
David Harris
a7204c9012 Removed unused DivSE from FPU 2022-12-26 07:29:19 -08:00
David Harris
fb0b2d4227 Moved floating-point tests earlier in Wally config 2022-12-25 22:31:20 -08:00
David Harris
cd47a7d781 testcount.pl script to count number of tests in each instruction 2022-12-25 22:28:58 -08:00
David Harris
7e77a39d32 Restored missing floating point load/store tests 2022-12-25 22:28:14 -08:00
David Harris
d627512d2b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-25 20:12:55 -08:00
Ross Thompson
4f436dc7f0 Added missing assignment for no branch predictor mode. 2022-12-24 17:08:29 -06:00
David Harris
0cc2b0fcd2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-24 12:24:38 -08:00
Ross Thompson
ded8f05602 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-24 14:24:25 -06:00
Ross Thompson
0d6ce1d459 Fixed bug with the performance counters not updating. 2022-12-24 14:24:17 -06:00
Ross Thompson
967d892088 Updated fpga constraints. 2022-12-24 10:21:16 -06:00
David Harris
10af4e4353 ALU cleanup 2022-12-24 07:18:35 -08:00
Alessandro Maiuolo
6740624f2d added finish message to setup 2022-12-23 22:53:39 -08:00
cturek
cc6f219bdd Added A Sign register. Fixed postprocessing logic for postinc and rem calculation. 2022-12-24 06:46:52 +00:00
Ross Thompson
b0d6c9616e Minor optimizations. 2022-12-23 20:11:36 -06:00
Ross Thompson
6e9d1eb180 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-23 19:51:23 -06:00
Katherine Parry
4b50ffac91 reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
Ross Thompson
6f9e21d61b Improved comment. 2022-12-23 15:13:15 -06:00
Ross Thompson
a2de53aeeb Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
fe9361de34 Removed XEnE, YEnE, and ZEnE from forward logic. 
Cleanup comments.
 2022-12-23 14:27:03 -06:00