Ross Thompson
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cf00f85456
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Updated vcu118 constraints to run cpu at 38.43Mhz.
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2022-11-15 10:19:38 -06:00 |
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Ross Thompson
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cc80f1f7b2
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Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s).
Increased CPU clock speed from 30 Mhz to 35 Mhz.
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2022-11-11 15:33:03 -06:00 |
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Ross Thompson
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d58a862f59
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Added new device trees for vcu118 and vcu108 boards.
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2022-10-24 17:45:10 -05:00 |
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Ross Thompson
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897982400c
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Updated the device tree to use 30Mhz instead of 10Mhz for the cpu timebase.
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2022-10-20 15:05:39 -05:00 |
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slmnemo
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a5d5bd272b
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changes suggested by ben, hopefully fixing buildroot (which is now not running)
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2022-05-20 18:42:38 -07:00 |
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bbracker
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871f63374e
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upgrade Buildroot Makefile to also copy over vmlinux
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2022-04-25 07:36:59 -07:00 |
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bbracker
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27920d3504
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less hardcoded paths in Makefile
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2022-04-21 20:42:02 -07:00 |
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David Harris
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5c607f2b6b
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Simplified profile for UART boot; added warnings on UART Rx errors
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2022-04-21 04:54:45 +00:00 |
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bbracker
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3aec080e15
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parsePlicState.py bugfix
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2022-04-13 13:04:43 -07:00 |
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bbracker
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52ed99ca1b
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improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
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2022-04-13 03:37:53 -07:00 |
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bbracker
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6c56f52e7c
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fix bugs in PLIC checkpoint state parsing
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2022-04-13 01:59:21 -07:00 |
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bbracker
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777de6e05b
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whoops fix address for PLIC int enables in checkpoint generation
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2022-04-13 01:36:09 -07:00 |
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bbracker
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3c1deb551d
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deprecate remove_dup.awk in favor of expanding parseGDBtoTrace.py to internally remove duplicates; this way the instruction counts in traps.txt are hopefully now in sync with the line numbers of all.txt
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2022-04-07 19:43:22 -07:00 |
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bbracker
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1e5e2704f7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-07 08:37:44 -07:00 |
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bbracker
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95438fca0d
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fix parseQEMUtoGDB.py to pass on interrupt messages correctly
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2022-04-07 04:47:15 -07:00 |
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kaveh Pezeshki
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7b85b39c48
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using -S for busybox objdump to provide source code snippets
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2022-04-06 23:06:49 +00:00 |
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bbracker
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241ec053e8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-06 07:50:57 -07:00 |
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bbracker
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c9c75d2e3e
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filter traps list down to just interrupts
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2022-04-06 07:49:44 -07:00 |
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bbracker
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241100c6ac
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change RAM size in genInitMem.sh
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2022-04-06 07:49:04 -07:00 |
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David Harris
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c22d6f2848
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Added bootmem source ccode
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2022-04-05 23:22:53 +00:00 |
|
David Harris
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4f7c37e406
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Changed Linux disassembly to -S to preserve source code lines
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2022-04-01 16:49:13 +00:00 |
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bbracker
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6fc54435c5
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checkpointSweep is bash-specific, so add shebang to make it so
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2022-03-28 13:40:50 -07:00 |
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bbracker
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2900117341
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fix genCheckpoint.sh binary memory dump
|
2022-03-27 20:54:59 -07:00 |
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bbracker
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6b812f33e1
|
change genCheckpoint.sh to only log 128MB of RAM
|
2022-03-27 19:16:39 -07:00 |
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bbracker
|
284f1ab75e
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fix parseGDBtoTrace.py to expect the CSRs that QEMU actually prints out
|
2022-03-27 19:05:44 -07:00 |
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bbracker
|
d1e4b61aa3
|
refactored buildroot configuration
|
2022-03-27 15:13:03 -07:00 |
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bbracker
|
6b2474a306
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-27 15:11:42 -07:00 |
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bbracker
|
3dcb87473b
|
change devicetree to expect only 128MB of RAM
|
2022-03-27 15:11:36 -07:00 |
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bbracker
|
b08066381a
|
fix multiple-context PLIC checkpoint generation
|
2022-03-25 01:02:22 +00:00 |
|
bbracker
|
9f60256f22
|
1st attempt at multiple channel PLIC
|
2022-03-24 17:08:10 -07:00 |
|
Ross Thompson
|
7fc128ba7c
|
added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.
|
2022-03-22 21:28:34 -05:00 |
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bbracker
|
e3303331ef
|
change genTrace to dump UART output to file so we can see how far parsing got
|
2022-03-08 09:52:17 -08:00 |
|
bbracker
|
51e68819c4
|
fix up PLIC and UART checkpointing
|
2022-03-07 23:48:47 -08:00 |
|
bbracker
|
9dbcdca433
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change UART state saving to temporarily modify LCR so that DLAB=0 when reading addresses 0 and 1 so that we get RBR and IER instead of divisor latch registers
|
2022-03-07 22:12:08 -08:00 |
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bbracker
|
52bfd65fd3
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change checkpoint generation to integrate GDB scripting more cleanly and save UART and PLIC state
|
2022-03-07 17:59:49 -08:00 |
|
bbracker
|
a93f36824d
|
modify debug.sh to not rely on external GDB script
|
2022-03-07 11:56:04 -08:00 |
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bbracker
|
74ff583f9b
|
add debug.sh
|
2022-03-07 19:52:19 +00:00 |
|
bbracker
|
01eeab2131
|
update checkpointSweep in accordance to having removed trace parsing feature
|
2022-03-06 14:55:51 -08:00 |
|
bbracker
|
c432e2175e
|
remove vestigial silencePipe mechanism
|
2022-03-06 14:54:35 -08:00 |
|
bbracker
|
ca6bb7c2d2
|
needed to initialize checkpoint directory
|
2022-03-06 14:51:25 -08:00 |
|
bbracker
|
6b1b471ca6
|
no longer use cythonization on python parser scripts because its a little complicated and has marginal benefit
|
2022-03-06 14:40:26 -08:00 |
|
bbracker
|
2e6fa01b9b
|
give genCheckpoint the same de-sudo'ing treatement
|
2022-03-06 14:37:12 -08:00 |
|
bbracker
|
675e112950
|
better to use $tvDir variable rather than abs path
|
2022-03-06 14:33:53 -08:00 |
|
bbracker
|
8720604bfc
|
replace sudo's with suggestions in genRecording.sh
|
2022-03-06 14:31:55 -08:00 |
|
bbracker
|
3e4ce15ea4
|
replace sudo's in genTrace.sh with suggested commands
|
2022-03-06 14:24:50 -08:00 |
|
bbracker
|
3e1f4decf1
|
small bugfix to suggested sudo commands for linux testvectors
|
2022-03-06 14:16:23 -08:00 |
|
bbracker
|
228f693f13
|
remove checkpoint trace generation since that requires qemu hacking and because we are able to generate the whole trace on VLSI
|
2022-03-06 14:04:30 -08:00 |
|
bbracker
|
f86e76a4b1
|
recommend sudo commands without automatically executing them in genInitMem.sh
|
2022-03-06 13:30:19 -08:00 |
|
bbracker
|
a0d0742227
|
change from clang to gcc when compiling testvector-generation executables
|
2022-03-06 13:18:53 -08:00 |
|
bbracker
|
94124cb108
|
add extractFunctionRadix step to buildroot Makefile
|
2022-03-05 19:02:07 -08:00 |
|