Ross Thompson
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f25de68b7d
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minor change to wave file.
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2021-02-19 09:08:13 -06:00 |
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Ross Thompson
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c6ebe7733b
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Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
About 149307ns of simulation run.
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2021-02-18 21:32:15 -06:00 |
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Ross Thompson
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de9e383bc6
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Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables.
Once combined with some simulation verilog this will display the current function in modelsim.
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2021-02-17 22:20:28 -06:00 |
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Ross Thompson
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5df7e959f3
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Integrated the branch predictor into the hardward. Not yet working.
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2021-02-17 22:19:17 -06:00 |
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Ross Thompson
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78db3654c6
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We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
This is not yet tested but the system verilog does compile.
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2021-02-15 14:51:39 -06:00 |
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Ross Thompson
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3ec1f668fc
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added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
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2021-02-14 15:13:55 -06:00 |
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Ross Thompson
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30df1cdd25
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The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
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2021-02-14 11:06:31 -06:00 |
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Teo Ene
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e878a8bed2
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After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to.
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2021-02-14 08:58:33 -06:00 |
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Shreya Sanghai
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30bfd7534c
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added branch tests
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2021-02-12 22:40:08 -05:00 |
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Teo Ene
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f25b372c32
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Quick commit for Ryan / branch / debugging.
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2021-02-12 16:06:02 -06:00 |
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Noah Boorstin
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423d3a53e5
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add reference output for some tests
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2021-02-12 18:33:24 +00:00 |
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bbracker
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9231646fb3
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bus rw bugfix and peripherals testing
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2021-02-12 00:02:45 -05:00 |
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Tejus Rao
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5158ca4220
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added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
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2021-02-11 13:38:38 -05:00 |
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Teo Ene
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dfb7333821
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-02-10 20:49:12 -06:00 |
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Teo Ene
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8a6de4fb86
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Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
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2021-02-10 20:48:39 -06:00 |
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Teodor-Dumitru Ene
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86fcaf0bb1
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Added hex code for the pre-compiled, provided, CoreMark binary
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2021-02-10 21:22:38 -05:00 |
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Teo Ene
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7ca03b2b38
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Added freshly compiled CoreMark binaries (elf) and hex code (memfile) for the following extensions:
- RV64I
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2021-02-10 20:12:07 -06:00 |
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ethan-falicov
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9edc4b6bfe
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Fixed merge conflict stuff
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2021-02-10 10:03:30 -05:00 |
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ethan-falicov
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7e8a58de1a
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More merge conflicts yay
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2021-02-10 09:54:30 -05:00 |
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ethan-falicov
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f778f464b7
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Merge conflict fixing
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2021-02-10 09:45:47 -05:00 |
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ethan-falicov
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06541260e0
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Adding I Type test cases from Lab 1
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2021-02-10 09:39:43 -05:00 |
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James E. Stine
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561ffcf56d
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Add ppt and mp4 of wavedrom usage
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2021-02-09 13:15:29 -06:00 |
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Jarred Allen
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403a0d033c
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Fix compile error in imperas testbench
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2021-02-07 15:48:12 -05:00 |
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Elizabeth Hedenberg
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81a1eb9a74
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merge conflict?
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2021-02-07 02:34:49 -05:00 |
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Jarred Allen
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48ade25577
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Actually run the WALLY-LOAD tests
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2021-02-06 14:56:40 -05:00 |
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Jarred Allen
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edd758453e
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Add test vector set for load instructions
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2021-02-06 13:05:59 -05:00 |
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James E. Stine
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5c017bac1f
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Updates to wavedrom
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2021-02-05 10:56:29 -06:00 |
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bbracker
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691d651fde
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JAL testing
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2021-02-05 08:08:42 -05:00 |
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James E. Stine
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eb468cc40f
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sorry ; last update
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2021-02-04 15:20:15 -06:00 |
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James E. Stine
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0eae86b6e3
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Update as overwrite a file :(
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2021-02-04 15:11:06 -06:00 |
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James E. Stine
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c259cd2e7e
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Updates to wavedrom for typos
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2021-02-04 14:49:17 -06:00 |
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James E. Stine
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a3bd34eb4b
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Add some example wavedrom files - more on the way including ppt
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2021-02-04 14:41:42 -06:00 |
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Thomas Fleming
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8588a1ed6b
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Complete STORE tests
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2021-02-04 15:38:22 -05:00 |
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Brett Mathis
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79cb7ed571
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Parallel FSR's and F CTRL logic
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2021-02-04 02:25:55 -06:00 |
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Jarred Allen
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ea791cb057
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Change busybear test to use work-busybear library
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2021-02-03 11:12:47 -05:00 |
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Jarred Allen
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743695400d
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Start on a test set for loads
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2021-02-03 00:37:43 -05:00 |
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David Harris
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91f6858de7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-02-02 19:44:43 -05:00 |
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David Harris
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a44c2abb12
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Minor tweaks
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2021-02-02 19:44:37 -05:00 |
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Jarred Allen
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10f023b44d
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Refactor regression test
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2021-02-02 17:22:29 -05:00 |
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Noah Boorstin
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b370be4a8a
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Add busybear testbench to nightly regression checking
If you don't like how I did this please feel free to undo it
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2021-02-02 22:05:35 +00:00 |
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Noah Boorstin
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00d9e13d68
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same thing but do that right this time
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2021-02-02 21:47:15 +00:00 |
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Noah Boorstin
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56ff32f857
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change undefined syntax in extend.sv
don't need verilator execption anymore
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2021-02-02 21:39:20 +00:00 |
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David Harris
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d56d7a75a6
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Rename ifu/dmem/ebu signals to match uarch diagram
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2021-02-02 15:09:24 -05:00 |
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David Harris
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aee44bb343
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Changed DTIM latency to 2 cycles
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2021-02-02 14:22:12 -05:00 |
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David Harris
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4fbb5f0f1b
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Cleaned up hazard interface
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2021-02-02 13:53:13 -05:00 |
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David Harris
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e661b32821
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-02-02 13:42:35 -05:00 |
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David Harris
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c23afbda3a
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Moved LoadStall generation to IEU
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2021-02-02 13:42:23 -05:00 |
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David Harris
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aad1d3d7dd
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Moved writeback pipeline registers from datapth into DMEM and CSR
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2021-02-02 13:02:31 -05:00 |
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Jarred Allen
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5090537f3c
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Fix intermittent errors caused by weird library stuff
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2021-02-02 11:20:09 -05:00 |
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Jarred Allen
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8dcb4b2d57
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Add the regression logs and new regression byproducts to the gitignore
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2021-02-02 10:43:41 -05:00 |
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