1427 Commits

Author	SHA1	Message	Date
David Harris	2b8e8707a7	Floating point test cleanup	2022-01-06 21:45:16 +00:00
David Harris	2b4c81fe98	Fixed unpacking bug; regression runs again	2022-01-06 18:22:30 +00:00
David Harris	55e757db03	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-06 18:10:32 +00:00
David Harris	c9aa21d5a3	FPU debug and configurable logic cleanup	2022-01-06 18:10:25 +00:00
Ross Thompson	d30ad136f3	cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.	2022-01-05 22:56:18 -06:00
Ross Thompson	365b2715ed	More name cleanup in cache.	2022-01-05 22:37:53 -06:00
Ross Thompson	77efcad15b	Changed names of address in caches. ... Removed old cache files.	2022-01-05 22:19:36 -06:00
Ross Thompson	5a2ae561a7	Updates to support fpga.	2022-01-05 18:07:23 -06:00
Ross Thompson	3517db6b64	Fixed xilinx synth error with $error in extend.sv	2022-01-05 17:48:08 -06:00
Ross Thompson	fb3207fc72	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-05 16:57:29 -06:00
Ross Thompson	8d33bf0b4a	Slower but correct implementation of flush.	2022-01-05 16:57:22 -06:00
David Harris	30c1ab5213	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-05 22:10:33 +00:00
David Harris	355efda9bc	Replaced exe2memfile with SiFive elf2hex	2022-01-05 22:10:26 +00:00
Ross Thompson	bd901cd125	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-05 14:15:27 -06:00
Ross Thompson	49eea2add5	Fixed bug with flush dirty not cleared in the correct cache line.	2022-01-05 14:14:01 -06:00
David Harris	85fa620cfb	Finished removing generate statements	2022-01-05 16:41:17 +00:00
David Harris	32590d484c	Removed more generate statements	2022-01-05 16:25:08 +00:00
David Harris	f04856ee94	Removed more generate statements	2022-01-05 16:01:03 +00:00
David Harris	c1d6550ccb	Removed generate statements	2022-01-05 14:35:25 +00:00
Ross Thompson	f89c1d91dc	Renamed most signals inside cache.sv so they are agnostic to i or d.	2022-01-04 23:52:42 -06:00
Ross Thompson	9eda7c12bd	the i and d caches now share common verilog.	2022-01-04 23:40:37 -06:00
Ross Thompson	b06c3b8acd	parameterized the caches with the goal of using common rtl for both i and d caches.	2022-01-04 22:40:51 -06:00
Ross Thompson	06168e67e4	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
Ross Thompson	d94a1c6404	Fixed bug where last line of dcache was not written back to memory on dcache flush.	2022-01-04 21:55:48 -06:00
Ross Thompson	3c3c6d0fe8	Fixed dcache flush.	2022-01-04 18:40:58 -06:00
David Harris	1f07470477	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 19:47:51 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00