257 Commits

Author	SHA1	Message	Date
Kevin Kim	efce306aab	removed redundant signals in controller	2023-03-03 21:52:25 -08:00
Kevin Kim	448e950eba	b controller generates comparison signed flag and controller branch signed logic updated accordingly	2023-03-03 17:12:29 -08:00
Kevin Kim	0bb75132c6	sltD signal debug. Passes regression	2023-03-03 12:44:33 -08:00
Kevin Kim	d24f74dc4b	sltD logic optimize	2023-03-03 12:35:40 -08:00
Kevin Kim	66b15b9163	Merge branch 'bctrlmigrate' of https://github.com/kipmacsaigoren/cvw into bctrlmigrate	2023-03-03 09:54:08 -08:00
Kevin Kim	0dee48fa5c	Merge branch 'openhwgroup:main' into bctrlmigrate	2023-03-03 09:53:59 -08:00
Kevin Kim	77c9114bcc	removed outdated b-signals in controller	2023-03-03 08:45:42 -08:00
Kevin Kim	2b9a6aba91	comments to bctrl	2023-03-03 08:41:47 -08:00
Kevin Kim	11f165d1bb	migrated B-subarith logic into b controller	2023-03-03 08:40:29 -08:00
Kevin Kim	b5a5f364e1	began subarith configurability optimization in controller	2023-03-03 08:27:11 -08:00
Ross Thompson	7dd8fa16c1	Renamed BTB misprediction to BTA.	2023-03-03 00:18:34 -06:00
Ross Thompson	bdab2c8506	Added divide cycle counter.	2023-03-02 23:59:52 -06:00
Ross Thompson	4b501f6e03	Added the i and d cache cycle counters.	2023-03-02 23:54:56 -06:00
Ross Thompson	b19d51b6a2	Added fence counter.	2023-03-02 23:29:20 -06:00
Ross Thompson	3dbfa96aef	Added csr write counter, sfence vma counter, interrupt counter, and exception counter.	2023-03-02 23:21:29 -06:00
Ross Thompson	cf4d8e6bd0	Added store stall to performance counters.	2023-03-02 23:10:54 -06:00
Ross Thompson	e257ec96ac	Reordered performance counters and added space for new ones.	2023-03-02 23:04:31 -06:00
Kevin Kim	f4b8968e12	bug fix, more elegant logic changes in controller	2023-03-02 16:00:56 -08:00
Kevin Kim	2a0c59d5a7	formatting	2023-03-02 15:28:43 -08:00
Kevin Kim	d0c486df54	removed main instruction decoder dependence on bmu controller	2023-03-02 15:28:33 -08:00
Kevin Kim	11a977ffe3	added bitmanip illegal instruction signal	2023-03-02 15:09:55 -08:00
Kevin Kim	b52208b539	zbc comments	2023-03-02 13:52:00 -08:00
Kevin Kim	2d7d143f6d	formatted bmu decoder	2023-03-02 13:45:15 -08:00
Kevin Kim	1b222f91be	moved ALUControlD into configurable block	2023-03-02 12:17:03 -08:00
Kevin Kim	1e1ecaafb1	moved SubArith and RegWriteE into configurable block	2023-03-02 12:15:57 -08:00
Kevin Kim	7dd4a2e975	added BRegWriteE signal	2023-03-02 12:15:22 -08:00
Kevin Kim	d40f3b2a1c	rename shifternew to shifter	2023-03-02 11:45:32 -08:00
Kevin Kim	905373d53b	zbc input select mux optimize	2023-03-02 11:43:05 -08:00
Kevin Kim	2bfbf051a5	zbc select mux optimization	2023-03-02 11:40:29 -08:00
Kevin Kim	44d40afca8	fixed controller lint, changed byte unit mux select name and input width	2023-03-02 11:36:12 -08:00
Kevin Kim	96995c5593	removed redundant zbs	2023-03-02 11:22:09 -08:00
Ross Thompson	3d1ffac7d7	Cleaned up branch predictor performance counters.	2023-03-01 17:05:42 -06:00
Ross Thompson	a61f8bc4cf	Set bp to use instruction class prediction by default.	2023-03-01 11:52:42 -06:00
Ross Thompson	e8744684cd	Branch predictor cleanup. ... I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.	2023-03-01 11:24:24 -06:00
Ross Thompson	08a1153ae9	More btb cleanup.	2023-03-01 10:47:00 -06:00
Ross Thompson	dd2433f7ff	Minor fix to btb.	2023-03-01 10:45:40 -06:00
Ross Thompson	2773048bd4	Name cleanup.	2023-02-28 17:48:58 -06:00
Kip Macsai-Goren	9e52ede0cd	Merge remote-tracking branch 'upstream/main' into bit-manip	2023-02-28 14:41:51 -08:00
Kip Macsai-Goren	2cab4a2f0a	Merge remote-tracking branch 'origin' into bit-manip	2023-02-28 14:39:57 -08:00
Ross Thompson	87013ccaf0	Found the performance bug with the branch predictor btb power saving update.	2023-02-28 15:57:34 -06:00
Ross Thompson	8af61c0cc0	Name changes to reflect diagrams.	2023-02-28 15:37:25 -06:00
Ross Thompson	a823d8d021	Undid the btb update as it reduces performance.	2023-02-28 15:21:56 -06:00
Kevin Kim	036cad71c6	bitmanip decoder spits out regwrite, w64, and aluop signals [NEEDS DEBUG]	2023-02-28 12:09:35 -08:00
Kevin Kim	6835a635cc	added BRegWrite, BW64, BALUOp signals to bctrl and controller ... -TODO: Main decode in bmuctrl must assert these 3 signals	2023-02-28 11:54:10 -08:00
Kevin Kim	82059fba67	changed shifter source select signal name	2023-02-28 11:41:40 -08:00
Kevin Kim	30ef1ac9e3	rename result back to ALUResult in ALU	2023-02-28 07:27:34 -08:00
Ross Thompson	3261f31e88	This icpred and btb changes are causing a performance issue.	2023-02-27 20:00:50 -06:00
Ross Thompson	69e8358639	Modified the BTB to save power by not updating when the prediction is unchanged.	2023-02-27 17:37:29 -06:00
Ross Thompson	44361f0a34	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-27 09:48:03 -06:00
David Harris	5c8fee127b	Added support for ZMMUL	2023-02-27 07:29:53 -08:00