Ross Thompson
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ef4c684336
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Added supervisor mode registers to tracer.
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2023-01-12 17:04:41 -06:00 |
|
Ross Thompson
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9917be817c
|
Added M CSRs to the CSRArray.
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2023-01-12 16:51:51 -06:00 |
|
Ross Thompson
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a68773eba1
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added machine csr to logger.
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2023-01-12 16:35:19 -06:00 |
|
Ross Thompson
|
2e622c9860
|
Added support to print the gprs.
|
2023-01-12 16:09:30 -06:00 |
|
Ross Thompson
|
4733b787f8
|
rvvi trace is coming alone nicely.
|
2023-01-12 14:46:31 -06:00 |
|
Ross Thompson
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3cc37e3f12
|
Completely stripped down imperas simulation.
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
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2023-01-12 12:48:38 -06:00 |
|
Ross Thompson
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2f2f3d6da5
|
Stripped out all signature checking.
Removed multiple tests loop.
Only runs 1 test now.
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2023-01-12 12:45:44 -06:00 |
|
Ross Thompson
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5ad0bacf5b
|
Created separate imperas testbench.
Resolved logger issue with the duplicated instructions after commit.
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2023-01-12 12:07:07 -06:00 |
|
Ross Thompson
|
94f24d3f58
|
Added instruction logger.
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2023-01-12 10:09:34 -06:00 |
|
Ross Thompson
|
6a616617d1
|
Restored to default configuration.
|
2023-01-09 00:21:45 -06:00 |
|
Ross Thompson
|
bf08c57ab0
|
Added branch outcome logger to testbench
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2023-01-07 13:16:57 -06:00 |
|
Ross Thompson
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f119b492bb
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2023-01-06 15:18:13 -06:00 |
|
Ross Thompson
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7223d1e05c
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Added python script to post process performance counter metrics.
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2023-01-06 15:15:54 -06:00 |
|
Ross Thompson
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09bb733088
|
Added code to print out performance counters at end of each test.
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2023-01-05 18:00:11 -06:00 |
|
Ross Thompson
|
0eceeeeeaa
|
Simiplified global history branch predictor.
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2023-01-04 23:41:55 -06:00 |
|
Katherine Parry
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95a1ddd636
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some commenting fixes, converter optimizations, and moves normshift into postproc
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2023-01-03 15:55:30 -06:00 |
|
Katherine Parry
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aca6f0d4e6
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removed ethe second bit from fma alignment shift
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2022-12-30 12:07:44 -06:00 |
|
Katherine Parry
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5844a596a3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-30 09:56:35 -06:00 |
|
David Harris
|
e9b314f902
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fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression
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2022-12-30 06:40:25 -08:00 |
|
Katherine Parry
|
90eb4fc1f1
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minor optimizations and renaming
|
2022-12-29 15:54:17 -06:00 |
|
Katherine Parry
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1b4fa38510
|
one bitt removed from inital lignment shift
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2022-12-28 17:46:53 -06:00 |
|
Cedar Turek
|
4ed2c6255c
|
idiv passing radix 2, four copies
|
2022-12-27 22:10:48 -08:00 |
|
David Harris
|
87abed6722
|
cleanup
|
2022-12-27 21:29:36 -08:00 |
|
David Harris
|
6cf73cdaee
|
Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M
|
2022-12-27 21:24:38 -08:00 |
|
David Harris
|
2de66e9eef
|
Moved fdivsqrtexpcalc to its own file
|
2022-12-26 08:45:43 -08:00 |
|
David Harris
|
7e77a39d32
|
Restored missing floating point load/store tests
|
2022-12-25 22:28:14 -08:00 |
|
Katherine Parry
|
4b50ffac91
|
reworked negitive sticky bit handeling in fma
|
2022-12-23 17:01:34 -06:00 |
|
Ross Thompson
|
98b824c4c4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-22 22:51:33 -06:00 |
|
Ross Thompson
|
206bc7daa6
|
Closing in on icache flushed by FlushD rather than TrapM.
|
2022-12-22 20:19:09 -06:00 |
|
Kip Macsai-Goren
|
a768d70093
|
Added status.tvm bit test that passes make and regression
|
2022-12-22 14:43:22 -08:00 |
|
David Harris
|
8bc753a291
|
Added assertion about atomics needing caches
|
2022-12-21 13:57:28 -08:00 |
|
Ross Thompson
|
3d95aa3423
|
Added timeout check to testbench.
A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
|
2022-12-21 09:18:00 -06:00 |
|
Ross Thompson
|
376b01fcb8
|
Attempted to make a cache test.
|
2022-12-18 17:15:08 -06:00 |
|
Ross Thompson
|
ebdac1a9d0
|
Updated tests for fpga and BP.
|
2022-12-18 16:24:26 -06:00 |
|
David Harris
|
2457448e29
|
Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
|
2022-12-15 08:23:34 -08:00 |
|
cturek
|
f57211bb49
|
Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
|
2022-12-10 21:56:35 +00:00 |
|
Kip Macsai-Goren
|
f486a763d9
|
Addded fix for 32 bit periph test and added test to regression
|
2022-12-06 09:56:08 -08:00 |
|
Kip Macsai-Goren
|
2dfa426e10
|
added passing GPIO test to 64 bit tests
|
2022-12-05 21:31:00 -08:00 |
|
Kip Macsai-Goren
|
c6c0ef05db
|
commented out periph test from wally32 periph so rv32ic doesn't hang
|
2022-12-05 20:23:16 -08:00 |
|
Kip Macsai-Goren
|
ae32e2a9ee
|
added passing tests to regression
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
282d06b45f
|
added -01 to all WALLY tests
|
2022-12-05 20:16:02 -08:00 |
|
Ross Thompson
|
128b3d20e7
|
Updated riscv arch test removed misaligned1.
|
2022-12-04 00:18:10 +00:00 |
|
Ross Thompson
|
de99663b97
|
Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
This reverts commit 70b89e5214.
|
2022-12-04 00:01:58 +00:00 |
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cturek
|
70b89e5214
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Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
|
2022-12-02 21:44:29 +00:00 |
|
David Harris
|
9c1b7e53e4
|
FPU divider working with execute stage stall
|
2022-12-02 11:11:53 -08:00 |
|
David Harris
|
4c6003d9e2
|
update test list
|
2022-12-02 04:28:47 -08:00 |
|
David Harris
|
ed39099405
|
reorder tests
|
2022-12-01 16:27:33 -08:00 |
|
David Harris
|
f64c0589fe
|
FPU test list
|
2022-12-01 10:18:36 -08:00 |
|
Ross Thompson
|
bfd238a4fc
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-30 13:30:37 -06:00 |
|
Ross Thompson
|
5e5cca6ae1
|
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
|
2022-11-30 11:01:25 -06:00 |
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