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Author SHA1 Message Date
James E. Stine
e913c1ea46 Modify testbench-fp.sv to handle parameterization as well some other minor mods. Have to make a better FPUActive desgination but for now works 2023-06-22 15:27:17 -05:00
James E. Stine
8f7ba2b8d2 For some reason this was modified - I probably made a mistake - put back vsim 2023-06-22 15:26:22 -05:00
James E. Stine
6d5d95b0f3 Remove path for cvw.sv so its found 2023-06-22 15:25:56 -05:00
Ross Thompson
4b3b590f21 Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits. 2023-06-22 12:55:49 -05:00
Ross Thompson
17b32f7dcc
Merge pull request #347 from kipmacsaigoren/unified_f_int_gen_fix 
fixed bug in combined intdivrem testvector extract script
 2023-06-22 12:38:45 -04:00
Kevin Kim
7e185a2f0d fixed bug in testvector extract script 
-old script skips first 2 lines in rv32m case, new script only skips first line
- prior code skipped every other line in the reference file, so it only generated half the test vectors, with half of them having the wrong answer
- prior code also opened test vector file to be written to in "append" mode, and I changed to write mode (so that the script overwrites instead of adding to an existing file)
 2023-06-22 09:13:22 -07:00
Ross Thompson
950577ed60
Merge pull request #346 from VictorClements/main 
FreeRTOS kernel submodule addin
 2023-06-21 18:26:42 -04:00
Victor Clements
27c933f3a0 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-06-21 09:02:02 -07:00
Ross Thompson
33c3383506
Merge pull request #345 from stineje/main 
Update sim-testfloat to fix errors due to bad config element.  I am n…
 2023-06-20 18:29:24 -04:00
James E. Stine
394c7ac9af Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file 2023-06-20 17:26:54 -05:00
Ross Thompson
626a918668 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
25103176a0 Updated fpga wave config. 2023-06-19 12:28:30 -05:00
Ross Thompson
8242544efa Updated fpga wally wrapper to work with the ILA. 2023-06-19 12:15:48 -05:00
Ross Thompson
1d2eb60ffb Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
Ross Thompson
faf09a89c2
Merge pull request #344 from davidharrishmc/dev 
Embench and coverage fixes
 2023-06-18 17:36:37 -04:00
David Harris
60931e7d5c Fixed embench to run all tests, even ones not in 1.0 2023-06-17 20:38:51 -07:00
harshinisrinath
dc6633c796 Improved testing of pmd in priv. 2023-06-16 17:13:54 -07:00
David Harris
7bea99aabb
Merge pull request #343 from harshinisrinath1001/main 
Improve test coverage on ieu fw.
 2023-06-16 16:11:51 -07:00
harshinisrinath
c9695e6813 Improve test coverage on ieu fw. 2023-06-16 16:09:48 -07:00
David Harris
e2f927b4e6 Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete 2023-06-16 16:07:28 -07:00
David Harris
95960620a2 Removed redundant and not-covered atomic check from StoreStallD 2023-06-16 16:05:53 -07:00
Ross Thompson
24b8c6c391 I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug. 2023-06-16 17:00:27 -05:00
Ross Thompson
4bee446cad Vivado requires an intermediate wrapper file for parameterization. 2023-06-16 16:30:14 -05:00
Ross Thompson
2f35bec970 FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
David Harris
dfedc13cfc erge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:32:37 -07:00
David Harris
281c036e70
Merge pull request #342 from ross144/main 
Testbench generates embench output files
 2023-06-16 10:32:18 -07:00
Ross Thompson
509aee36ef Modified the testbench to generate the required files for embench scripts. 2023-06-16 12:27:22 -05:00
David Harris
2d94800ad7 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:03:48 -07:00
David Harris
1cb0cf38b4
Merge pull request #341 from ross144/main 
Fix embench so it does not crash
 2023-06-16 10:03:41 -07:00
Ross Thompson
3f628d6bf2 embench testbench no longer crashes. 2023-06-16 11:54:41 -05:00
David Harris
3c98ed9e29 Added assertions for ZICNTR and ZIHPM 2023-06-16 09:26:02 -07:00
David Harris
557e991376
Merge pull request #340 from eroom1966/main 
Incorporate changes for IDV
 2023-06-16 09:04:55 -07:00
David Harris
a5b6c5b96d
Merge pull request #339 from ross144/main 
Fixed imperas testbench to work with parameters
 2023-06-16 09:04:39 -07:00
eroom1966
9125f25880 add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
Lee Moore
98d2ab8160
Merge pull request #4 from ross144/main 
PR from Ross
 2023-06-16 15:24:07 +01:00
Ross Thompson
c26845e9ec Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-16 08:59:59 -05:00
Ross Thompson
605ddf7990 Fixed the imperas testbench to work with parameters. 2023-06-16 08:59:52 -05:00
David Harris
cfecd48752
Merge pull request #338 from ross144/main 
First pass at testbench restructuring
 2023-06-15 14:36:28 -07:00
Ross Thompson
110a41c046 Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
6d31936e89 Added comment to uart LCR to check reset value after updating FPGA. 2023-06-15 15:39:51 -05:00
Ross Thompson
34d1d50b87 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
a011b7d591 Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
7278e0b2cc
Merge pull request #333 from davidharrishmc/dev 
cvw.sv moved to root to avoid warnings; UART cleanup and QEMU removal
 2023-06-15 16:28:21 -04:00
Ross Thompson
a55bcad5c1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
Ross Thompson
3c4677ef63 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
David Harris
52ab586a9d Added input gating on FPU 2023-06-15 12:38:33 -07:00
David Harris
524d8e8469 Gated MDU to save power; doesn't seem to have affected simulation time 2023-06-15 12:17:23 -07:00
David Harris
c7d06382b3 Bit manipulation comment cleanup 2023-06-15 12:16:46 -07:00
Ross Thompson
e3cf1419ed Deleted remaining old configs except fpga as I still need to create the parameterized version. 2023-06-15 14:08:13 -05:00
Ross Thompson
44c72c20e2 Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00