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1296 Commits

Author SHA1 Message Date
David Harris
9e21358d75 Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
David Harris
0a7ed944a5 Revert to 98b824 2022-12-22 23:58:14 -08:00
David Harris
56312cd0a6 Clean up unused FPU signals 2022-12-22 23:53:09 -08:00
David Harris
4d509f94ec FDIV merge 2022-12-22 23:03:03 -08:00
David Harris
2d72bed1f4 Removed unused signals in FPU and CSR 2022-12-22 22:59:05 -08:00
Ross Thompson
98b824c4c4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-22 22:51:33 -06:00
Ross Thompson
2cc4d66ded Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
03021765a6 The LSU is properly using FlushW rather than TrapM. 2022-12-22 21:47:34 -06:00
Ross Thompson
3b791b768a Success we've replaced TrapM with FlushD in the IFU. 2022-12-22 21:36:49 -06:00
Ross Thompson
e0e92952c3 Partial cleanup for BP. 2022-12-22 20:33:38 -06:00
Ross Thompson
206bc7daa6 Closing in on icache flushed by FlushD rather than TrapM. 2022-12-22 20:19:09 -06:00
Ross Thompson
41fe876e7a First pass at resolving ifu flush on trap rather than FlushD. 2022-12-22 15:53:06 -06:00
David Harris
d4bedca1bf Code cleanup 2022-12-22 10:04:50 -08:00
cturek
ccbad67497 Added negative-result int diviison support in U and UM registers. 13 tests pass! 2022-12-22 16:25:37 +00:00
cturek
1b7ed72ece Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00
cturek
3574bedb08 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-22 05:45:00 +00:00
cturek
80ca75e216 Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc. 2022-12-22 05:44:55 +00:00
David Harris
c42967f5c6 XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-21 20:39:38 -08:00
Ross Thompson
c8c73f47d2 CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled. 2022-12-21 22:13:05 -06:00
cturek
0b4d81bd4a worked out some bugs with int div cycles 2022-12-22 02:22:01 +00:00
cturek
c3fdc0ab23 Renamed signals to E and M stages, forwarded preprocessed n to fsm 2022-12-22 00:43:27 +00:00
Ross Thompson
84f8d9953f Updated cache fsm names to match book. 2022-12-21 16:49:53 -06:00
Ross Thompson
d72cf65809 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-21 16:13:09 -06:00
Ross Thompson
e7a44d8975 Changed GatedStallF to GatedStallD. 2022-12-21 16:12:55 -06:00
David Harris
d0a3e939e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-21 14:12:25 -08:00
cturek
0c30ecf86d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 20:41:38 +00:00
David Harris
6d46261350 comment cleanup 2022-12-21 12:39:09 -08:00
David Harris
c7f3aae084 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
cturek
ab71962dc0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 19:35:57 +00:00
cturek
c479b9f112 fixed normshift calculations 2022-12-21 19:35:47 +00:00
David Harris
5ef3a1d371 git push 
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
 2022-12-21 11:31:27 -08:00
David Harris
e327d70cdc Removed unused FPU signals 2022-12-21 11:31:22 -08:00
Ross Thompson
c3b43b2fac Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
0b4186f1e8 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
Ross Thompson
91f948a91c The optimzied PC+2/4 logic still hanges on wally32priv. 2022-12-21 09:19:34 -06:00
Ross Thompson
6858b7568c Renamed PCPlusUpperF to PCPlus4F. 2022-12-21 09:18:30 -06:00
Ross Thompson
ac94b55e74 Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. 
Switched to even simplier PC+2/4 logic.
 2022-12-21 09:00:09 -06:00
Ross Thompson
fe723af1af Comments about PC+2/4. 2022-12-21 08:35:43 -06:00
David Harris
5d91b3044f Clean up vecgtored interrupts 2022-12-20 16:53:09 -08:00
David Harris
dd0a02f0c8 Converted tvecmux to structural 2022-12-20 16:24:04 -08:00
Ross Thompson
f860440361 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 18:09:37 -06:00
Ross Thompson
80be2e7be5 privileged pc mux cleanup. 2022-12-20 18:05:44 -06:00
Ross Thompson
97593e8a6f Moved privileged pc logic into privileged unit. 2022-12-20 17:55:45 -06:00
David Harris
8f640f050f IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI 2022-12-20 15:38:30 -08:00
Ross Thompson
35ad49502f Implement FENCE.I as NOP when ZIFENCEI is not supported. 2022-12-20 17:34:11 -06:00
Ross Thompson
0dc09ac22d Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 17:11:35 -06:00
Ross Thompson
65cbff9283 Changed long names of vectored pcm signals. 2022-12-20 17:01:20 -06:00
David Harris
f3e9950317 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-20 14:43:33 -08:00
David Harris
e7702e48b7 FPU remove unused signals 2022-12-20 14:43:30 -08:00
Ross Thompson
6f543d01b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 16:36:44 -06:00
Ross Thompson
8029b12f2a Renumbered bits for PCPlusUpper. 2022-12-20 16:33:49 -06:00
David Harris
caef1a6997 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-20 11:23:53 -08:00
David Harris
f0ef5caf32 Memory cleanup 2022-12-20 11:22:26 -08:00
Ross Thompson
c4901450c4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 12:58:59 -06:00
Ross Thompson
684d260005 Reorganized IFU PCNextF logic. 2022-12-20 12:58:54 -06:00
David Harris
e74d47bcb4 Renamed renamed sram to ram 2022-12-20 08:36:45 -08:00
David Harris
16f3c25cb7 sram1p1rw cleanup 2022-12-20 02:57:51 -08:00
David Harris
08234cb1c7 Remoed unused bram modules 2022-12-20 02:40:45 -08:00
David Harris
2c46f22be5 Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:55 -08:00
David Harris
54e856c4f5 Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:36 -08:00
David Harris
caf457106a Replaced || and && with single ops 2022-12-20 01:33:35 -08:00
Ross Thompson
dedc08bd42 several options for pcnextf on fence.i 2022-12-19 23:33:12 -06:00
Ross Thompson
2df18cc758 More bp/ifu pcmux cleanup. 2022-12-19 23:16:58 -06:00
Ross Thompson
565585b35a Moved more muxes inside bp. 2022-12-19 22:51:55 -06:00
Ross Thompson
d8ee0ea59d Begin cleanup of ifu. partial move of pc muxes inside bp. 2022-12-19 22:46:11 -06:00
David Harris
9fea16fd20 Simplified InstrRawD register 2022-12-19 15:18:42 -08:00
David Harris
a4da3f30e1 Explained hazard causes 2022-12-19 09:41:41 -08:00
David Harris
67763dbeec Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-19 09:09:57 -08:00
David Harris
3172dfd6a9 Properly decode fcvtint to prevent unnecessary stalls 2022-12-19 09:09:48 -08:00
Ross Thompson
159eda85f0 Renamed FStallD to FPUStallD. 2022-12-19 09:28:45 -06:00
Alessandro Maiuolo
5a82898649 Added NumZeroE, AZeroM, and BZeroM 2022-12-18 20:02:40 -08:00
Alessandro Maiuolo
2989782fe6 fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8) 2022-12-18 19:04:36 -08:00
Ross Thompson
4f56e6ff5d I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
Ross Thompson
73fd3fe040 Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back. 2022-12-17 23:47:49 -06:00
Ross Thompson
cdeccd78e6 At long last found the subtle bug in the LRU. 
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
 2022-12-17 10:03:08 -06:00
Ross Thompson
ade06f3780 Fixed a bug with the new cache flush changes. 2022-12-16 19:28:32 -06:00
Ross Thompson
7d04675073 Cleanup comments. 2022-12-16 17:08:35 -06:00
Ross Thompson
89a30e7e37 Further cleanfsm cleanup. 2022-12-16 16:37:45 -06:00
Ross Thompson
9ebea891e2 More cachefsm cache flush cleanup. 2022-12-16 16:32:21 -06:00
Ross Thompson
731fbfc851 Oups found a bug with the new flush cache states. 2022-12-16 16:22:40 -06:00
Ross Thompson
41c636ecfa Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-16 15:37:03 -06:00
Ross Thompson
b462554896 Cleanup of cache flush fsm enhancement. 2022-12-16 15:36:53 -06:00
Ross Thompson
dacba855da Rough draft of cache flush fsm enhancement. 2022-12-16 15:28:22 -06:00
cturek
4b8cbd9fa0 Added integer support for initC 2022-12-16 19:02:11 +00:00
cturek
06c58f310d Added mux for integer special case, renamed signals to match pipelined stage 2022-12-16 18:43:49 +00:00
David Harris
378c40002f Clean up interrupt masking by Commit 2022-12-16 08:27:39 -08:00
David Harris
7989f449ad Disabled starting FPU divider when IDIV_ON_FPU = 0 2022-12-16 06:35:29 -08:00
cturek
d7571bb9b1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-16 03:41:39 +00:00
David Harris
b7abc0037e Use FlushE to reset integer divider FSM 2022-12-15 11:00:54 -08:00
David Harris
4365c99b52 Refactored stalls and flushes, including FDIV flush with FlushE 2022-12-15 10:56:18 -08:00
David Harris
2457448e29 Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE 2022-12-15 08:23:34 -08:00
Ross Thompson
fa19a111c6 Hazard cleanup. 2022-12-15 10:05:17 -06:00
Ross Thompson
e774dd2db9 Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage. 2022-12-15 09:53:35 -06:00
Ross Thompson
b02550b05c Merge branch 'main' into hazards 2022-12-15 08:44:59 -06:00
David Harris
33aca5d35e Added IDIV_ON_FPU flag to control whether integer division uses FPU 2022-12-15 06:37:55 -08:00
David Harris
5f637ef4a7 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
cturek
8829e627eb Fixed BZero and initU/initUM muxes 2022-12-14 16:44:46 +00:00
Ross Thompson
09dcb56217 Signal renames to reflect figures. 2022-12-14 09:49:15 -06:00
Ross Thompson
a3ec829b80 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-14 09:34:34 -06:00
Ross Thompson
6da7849d27 Reduced complexity of linebytemask. 2022-12-14 09:34:29 -06:00