David Harris 4365c99b52 Refactored stalls and flushes, including FDIV flush with FlushE		2022-12-15 10:56:18 -08:00
..
cache	Signal renames to reflect figures.	2022-12-14 09:49:15 -06:00
ebu	Changed CPUBusy to Stall in ebu modules.	2022-12-11 15:51:35 -06:00
fpu	Refactored stalls and flushes, including FDIV flush with FlushE	2022-12-15 10:56:18 -08:00
generic	Intermediate commit. Replaced flip flop dirty bit array with sram.	2022-11-30 00:08:31 -06:00
hazard	Refactored stalls and flushes, including FDIV flush with FlushE	2022-12-15 10:56:18 -08:00
ieu	Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.	2022-12-15 09:53:35 -06:00
ifu	Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.	2022-12-15 09:53:35 -06:00
lsu	Renamed CPUBusy in LSU.	2022-12-11 15:52:51 -06:00
mmu	Moved CPUBusy out of HPTW.	2022-12-11 15:48:00 -06:00
muldiv	Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE	2022-12-15 08:23:34 -08:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
uncore	Fixed the uart transmit fifo overrun bug.	2022-10-26 14:48:09 -05:00
wally	Refactored stalls and flushes, including FDIV flush with FlushE	2022-12-15 10:56:18 -08:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00