Ross Thompson
0e9e561726
Updated .gitignore file to hide fpga outputs.
2021-12-13 18:30:10 -06:00
David Harris
19fb0aace8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-04 20:26:01 -08:00
David Harris
83765ea3bc
Added files to repo
2021-12-04 20:25:33 -08:00
Ross Thompson
7f52d86980
Added make clean to fpga IP generator.
2021-11-29 18:42:28 -06:00
Ross Thompson
1117b90f40
Created Makefile to manage IP generation.
2021-11-29 18:33:58 -06:00
bbracker
8563c0f016
linux testgen refactor
2021-11-01 14:09:49 -07:00
bbracker
ca61d9b6b8
gitignore the addins folder because it contains external repos
2021-10-19 13:32:26 -07:00
bbracker
f2cab415b2
gitignore new logs folder
2021-10-12 10:42:13 -07:00
bbracker
56f246463f
separated buildroot debugging from buildroot logging
2021-07-17 14:52:34 -04:00
bbracker
04ce2f7256
testvector unlinker for dev purposes
2021-07-14 11:05:34 -04:00
bbracker
eb8c1bf5e7
needed to create a directory for gdb script
2021-07-13 19:39:57 -04:00
bbracker
90eb84cc61
updated buildroot make procedure to incorporate configs more robustly
2021-07-13 12:40:14 -04:00
bbracker
b2cb86d55c
organize/update buildroot scripts for new image
2021-07-09 17:03:47 -04:00
bbracker
5736fdecbb
organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files
2021-07-08 19:18:11 -04:00
bbracker
59b2a49854
split intermediate GDB output file into smaller files for better debug experience
2021-06-26 07:18:26 -04:00
bbracker
3ae4cd951a
make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
2021-06-24 08:35:00 -04:00
bbracker
56b0d4d016
added slack notifier for long sims
2021-06-22 08:31:41 -04:00
bracker
3d99c9c2c4
gitignore merge
2021-06-18 21:12:05 -05:00
bracker
ed75172f21
handle tera usernames more gracefully
2021-06-18 21:11:14 -05:00
bbracker
10ca2ac5bc
on-Tera solution for sym linking to linux testvectors
2021-06-18 22:01:18 -04:00
bracker
a9f9ef1180
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 20:41:01 -05:00
bracker
8a8b0dcfd7
script support for copying large files from tera
2021-06-18 20:40:19 -05:00
bbracker
7de660f8aa
still not sure if QEMU workaround is correct, but here is all linux progress so far
2021-06-17 00:50:02 -04:00
bbracker
c08f5e6732
script for running make and logging output
2021-05-17 22:12:18 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Noah Boorstin
0e71c212b2
buildroot parser: more updates
...
5 -> 23 instructions!
2021-04-17 17:44:46 -04:00
Ross Thompson
1e83810450
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Noah Boorstin
ed37e933e5
busybear: stop NOPing out atomics
...
and bump regression to check for 800k instrs, up from 200k
2021-03-25 13:29:56 -04:00
Thomas Fleming
95bf1e26b8
Add vscode and pycache folders to .gitignore
2021-03-25 02:37:50 -04:00
bbracker
77768cee5d
gitignore FunctionRadix.addr
2021-03-25 00:13:46 -04:00
Ross Thompson
149c9aa0f2
Added debug option to disable the function radix if not needed.
...
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 15:17:02 -06:00
Noah Boorstin
a5f1dbfe23
add .nfs* files to gitignore
2021-02-28 20:48:01 +00:00
Jarred Allen
b57604f4e4
Add the regression logs and new regression byproducts to the gitignore
2021-02-02 10:43:41 -05:00
Noah Boorstin
be3d024527
Busybear test now processes first 100 instrs correctly!
...
- changed test parser to recognize lw in addition to lw
also, added temporary questa files (wlft*) to .gitignore
2021-01-28 01:19:27 -05:00
Noah Boorstin
6d88c57f0f
load instructions from file line by line
2021-01-22 14:11:17 -05:00
Noah Boorstin
3f2820646d
More testbench setup work
...
- Copy bare-bones testbench from E85
- have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier
- Create .gitignore for vsim files
- Make PC reset a macro, change to 0x1000 to conform to the bootloader
I don't know a good way to put the linux register trace file we're generating on git,
since its both nontrivial to make and way to big to keep in a git repo
for now it lives in /mnt/scratch/riscv_testbench/
2021-01-21 17:55:05 -05:00
