Ross Thompson
5acdf541b9
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
9849983348
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
4a0e4aed99
Signal renames to reflect figures.
2022-12-14 09:49:15 -06:00
Ross Thompson
9bf0eedf73
Optimized way selection logic.
2022-12-04 12:30:56 -06:00
Ross Thompson
3442b04f9e
Properly flush cacheLRU.
2022-12-01 17:32:58 -06:00
Ross Thompson
b5718c9baa
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
2022-11-29 14:51:09 -06:00
Ross Thompson
96cc4c7ebe
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
78acd40424
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
279f5bc615
Cleanup cacheLRU.
2022-11-22 14:59:01 -06:00
Ross Thompson
e1dbe58632
File name change for cachereplacement policy to cacheLRU
2022-11-20 22:35:02 -06:00
