David Harris
57e1111df3
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
David Harris
cc04009f82
Touched up TLB D and A bit checks
2021-07-04 18:17:09 -04:00
David Harris
595df47a3e
Fixed TLB_ENTRIES merge conflict and handling of global PTEs
2021-07-04 18:05:22 -04:00
David Harris
71268cc0e8
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:53:08 -04:00
David Harris
6b9cfe90d8
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:52:00 -04:00
Ross Thompson
8e48865140
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:19:39 -05:00
David Harris
d138d6545d
Restructured TLB Read as AND-OR operation with one-hot match/read line
2021-07-04 17:01:22 -04:00
David Harris
b59213c83f
Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders
2021-07-04 16:33:13 -04:00
David Harris
deae60eb1d
TLB cleanup
2021-07-04 14:59:04 -04:00
David Harris
243c03f870
TLB cleanup
2021-07-04 14:37:53 -04:00
David Harris
fed096407b
TLB minor organization
2021-07-04 14:30:56 -04:00
David Harris
a5c0dc8c81
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
5b891e05ac
TLB mux and swizzling cleanup
2021-07-04 12:53:52 -04:00
David Harris
622060b99f
Replaced generates with arrays in TLB
2021-07-04 12:32:27 -04:00
David Harris
b5df9b282d
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
David Harris
9276446797
Switched to array notation for pmpchecker
2021-07-04 10:51:56 -04:00
David Harris
c897bef8cd
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
Ross Thompson
9b959715a0
removed mmustall and finished port annotations on ptw and lsuArb.
2021-07-03 16:06:09 -05:00
David Harris
ee605d7550
Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
2021-07-03 03:29:33 -04:00
David Harris
d3dedc1637
Cleaned up PMA/PMP checker unused code
2021-07-03 02:25:31 -04:00
Ross Thompson
16e672ada0
Fixed up the physical address generation for 64 bit page table walker.
2021-07-02 15:49:32 -05:00
Ross Thompson
a8fbbb0631
Fixed up the bit widths on the page table walker for rv32.
2021-07-02 15:45:05 -05:00
Ross Thompson
46831035fb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-02 13:56:49 -05:00
David Harris
648c09e5ef
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:04:13 -04:00
Ross Thompson
386193de00
added page table walker fault exit for icache.
2021-07-01 17:59:55 -05:00
Ross Thompson
3dae02818c
OMG. It's working!
2021-07-01 17:37:53 -05:00
Ross Thompson
9139cd2954
Fixed tab space issue.
2021-07-01 17:17:53 -05:00
Ross Thompson
c3eaa3169e
Fixed the wrong virtual address write into the dtlb.
2021-07-01 16:55:16 -05:00
Ross Thompson
9d9415ea67
Got some stores working in virtual memory.
2021-07-01 12:49:09 -05:00
Ross Thompson
4530e43df6
The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
2021-06-30 17:02:36 -05:00
Ross Thompson
07a0b66fdf
Major rewrite of ptw to remove combo loop.
2021-06-30 16:25:03 -05:00
Ross Thompson
b31e0afc2a
The icache now correctly interlocks with the PTW on TLB miss.
2021-06-30 11:24:26 -05:00
Ross Thompson
2598f08782
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Ross Thompson
ae6140bd94
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
Kip Macsai-Goren
389b9a510e
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Ross Thompson
732551d6be
Fixed combo loop in between the page table walker and i/dtlb.
2021-06-24 13:47:10 -05:00
Kip Macsai-Goren
547bf1d0af
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
6134c22aca
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
David Harris
718630c378
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
4189b2d4a7
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
1972d83002
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6dc54acde8
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
Kip Macsai-Goren
d6c5c61b59
Fixed mask assignment error, made usage, variables more clear
2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
b78c09baed
Continued fixing fsm to work right with svmode
2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
852bb9296f
updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop
2021-06-22 11:21:11 -04:00
David Harris
29ad38fb9e
Added Physical Address and Size to PMA Checker/MMU
2021-06-21 01:27:02 -04:00
David Harris
aef408af58
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
David Harris
a3f3533cce
Changed physical addresses to PA_BITS in size in MMU and TLB
2021-06-18 09:11:31 -04:00
David Harris
cc78504ae4
Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX
2021-06-18 08:13:15 -04:00
David Harris
72d8d34e3c
allow all size memory access in CLINT; added underscore to peripheral address symbols
2021-06-18 08:05:50 -04:00
