Ross Thompson
b6ae6fea27
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
573ff47763
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00
David Harris
453a794f86
Testbench directory cleanup
2022-01-07 17:02:16 +00:00
David Harris
3d2671a8b0
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
913a78323c
moved proposed-sdc
2022-01-07 12:44:21 +00:00
David Harris
6c0cd5ef20
piplined directory cleanup
2022-01-07 12:43:50 +00:00
David Harris
8481c93e1b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-07 05:39:16 +00:00
Ross Thompson
de3bbd3fe0
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
David Harris
261882bf78
Used .* in wrapper
2022-01-07 05:23:42 +00:00
Ross Thompson
fa0080ca70
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
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assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
2df92af488
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
27c1d73cb1
Code cleanup
2022-01-07 04:07:04 +00:00
Ross Thompson
5402b55c44
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 17:19:20 -06:00
Ross Thompson
0438975e27
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
David Harris
0c8d556311
Tests cleanup:
2022-01-06 23:07:22 +00:00
David Harris
6fafabbfad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 23:04:33 +00:00
David Harris
53637049b7
Makefile make allclean
2022-01-06 23:04:30 +00:00
David Harris
ae64b859c3
Fixed multiplier nan boxing bug
2022-01-06 23:03:29 +00:00
Katherine Parry
631d05dcdc
some FPU test fixes
2022-01-06 23:03:20 +00:00
Ross Thompson
e0740034f0
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
David Harris
3bfe23bc75
More FP unpacking fix
2022-01-06 22:22:22 +00:00
David Harris
770780e394
Floating point test cleanup
2022-01-06 21:45:16 +00:00
David Harris
a5a89e58a8
Fixed unpacking bug; regression runs again
2022-01-06 18:22:30 +00:00
David Harris
eff9cec415
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 18:10:32 +00:00
David Harris
aca26de498
FPU debug and configurable logic cleanup
2022-01-06 18:10:25 +00:00
Ross Thompson
f604a0d79e
cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.
2022-01-05 22:56:18 -06:00
Ross Thompson
a4afc1bc54
More name cleanup in cache.
2022-01-05 22:37:53 -06:00
Ross Thompson
e74e8c2e86
Changed names of address in caches.
...
Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
1ab3a17ff7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
Ross Thompson
9ea34e390a
Fixed xilinx synth error with $error in extend.sv
2022-01-05 17:48:08 -06:00
Ross Thompson
de32930e63
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 16:57:29 -06:00
Ross Thompson
da585b30f9
Slower but correct implementation of flush.
2022-01-05 16:57:22 -06:00
David Harris
fed44cf9cf
Reinstated many arch f/d tests that had failed because of memfile issues
2022-01-05 22:44:10 +00:00
David Harris
8305eb80ff
Restored many of the arch32f and arch64d that had been failing because of memfile issues
2022-01-05 22:23:46 +00:00
David Harris
90dd961ea5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-05 22:10:33 +00:00
David Harris
07932ad0aa
Replaced exe2memfile with SiFive elf2hex
2022-01-05 22:10:26 +00:00
Ross Thompson
0310df96a4
Changes to wave file.
2022-01-05 14:16:59 -06:00
Ross Thompson
7086a0ed08
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 14:15:27 -06:00
Ross Thompson
cc51a27a34
Fixed bug with flush dirty not cleared in the correct cache line.
2022-01-05 14:14:01 -06:00
David Harris
d17a305538
Finished removing generate statements
2022-01-05 16:41:17 +00:00
David Harris
6d4714651c
Removed more generate statements
2022-01-05 16:25:08 +00:00
David Harris
da5ead23bf
Removed more generate statements
2022-01-05 16:01:03 +00:00
David Harris
d66f7c841b
Removed generate statements
2022-01-05 14:35:25 +00:00
Ross Thompson
98be8201b2
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
Ross Thompson
fffaf654e6
the i and d caches now share common verilog.
2022-01-04 23:40:37 -06:00
Ross Thompson
13dbf3cc0f
parameterized the caches with the goal of using common rtl for both i and d caches.
2022-01-04 22:40:51 -06:00
Ross Thompson
888a60d8d6
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
Ross Thompson
cb301a78ad
Fixed bug where last line of dcache was not written back to memory on dcache flush.
2022-01-04 21:55:48 -06:00
Ross Thompson
101a8bdb5b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-04 18:41:52 -06:00
Ross Thompson
ecc7bf5237
Fixed dcache flush.
2022-01-04 18:40:58 -06:00
David Harris
9ddc6db0a6
Removed imperas mmu tests; using wallypriv instead
2022-01-04 23:14:53 +00:00
Kip Macsai-Goren
c65fc4d5e6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 21:30:51 +00:00
Kip Macsai-Goren
46b0cb810d
fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh.
2022-01-04 21:30:38 +00:00
David Harris
0a7ec3e58d
Fixed bad address for F/fmsub_b18-01
2022-01-04 21:04:06 +00:00
David Harris
d1a7416028
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
