Ross Thompson
b5bcb5437f
Merge branch 'main' of github.com:ross144/cvw
2023-08-02 16:51:42 -05:00
Ross Thompson
087d418c35
Updateds to vcu118 constraints and device tree.
2023-08-02 16:51:32 -05:00
Ross Thompson
dd41f52292
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-08-01 12:57:20 -05:00
Jacob Pease
b56a8f9cf7
Updated driver for latest version of linux
2023-08-01 12:56:16 -05:00
Ross Thompson
eb5fb07f54
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-08-01 11:04:26 -05:00
Jacob Pease
78ea821f2c
Updated linux and buildroot configs initial commit.
2023-08-01 10:55:46 -05:00
Ross Thompson
1b237a14a1
Pushed performance of arty a7 to 23Mhz.
2023-07-31 14:13:09 -05:00
Jacob Pease
d3476b64cd
Updated VCU108 device tree for 256MB memory.
2023-07-27 17:44:31 -05:00
Ross Thompson
8dc7870e62
Updated Arty A7 fpga config and device tree to 256MiB main memory.
2023-07-25 15:11:47 -05:00
Ross Thompson
d418e4fa5e
Updated arty a7 device clock speed for 20Mhz.
2023-07-24 11:50:00 -05:00
Ross Thompson
fd187e9ee6
Merge branch 'main' of github.com:ross144/cvw
2023-07-24 10:47:05 -05:00
Ross Thompson
d239b0649e
Improved timing constraints for arty a7 to push clock speed to 20Mhz.
2023-07-24 10:46:49 -05:00
Ross Thompson
608400ac6a
Updated arty a7 device tree.
2023-07-21 19:08:45 -05:00
Ross Thompson
6e17cfba03
At least it simulates and gets through fpga elaboration.
2023-07-21 18:40:26 -05:00
Ross Thompson
3eeecd2f27
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
37078f3d9b
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
Jacob Pease
36785848a5
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
3bf2b35704
Wow. The newest version of Vivado does not like the enums as parameters.
...
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Ross Thompson
a5f75d568b
Added artya7 device tree.
2023-07-17 16:01:02 -05:00
Jacob Pease
142ec857ed
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
Ross Thompson
3de5144ae4
Updated vcu118 constraints to run cpu at 38.43Mhz.
2022-11-15 10:19:38 -06:00
Ross Thompson
b812549f38
Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s).
...
Increased CPU clock speed from 30 Mhz to 35 Mhz.
2022-11-11 15:33:03 -06:00
Ross Thompson
2e60edaedd
Added new device trees for vcu118 and vcu108 boards.
2022-10-24 17:45:10 -05:00
Ross Thompson
d68bdfbade
Updated the device tree to use 30Mhz instead of 10Mhz for the cpu timebase.
2022-10-20 15:05:39 -05:00
slmnemo
e3a7e3e2f3
changes suggested by ben, hopefully fixing buildroot (which is now not running)
2022-05-20 18:42:38 -07:00
bbracker
6f63b88c60
upgrade Buildroot Makefile to also copy over vmlinux
2022-04-25 07:36:59 -07:00
bbracker
cd70175e5a
less hardcoded paths in Makefile
2022-04-21 20:42:02 -07:00
David Harris
1e19cf9f14
Simplified profile for UART boot; added warnings on UART Rx errors
2022-04-21 04:54:45 +00:00
bbracker
20c82b6f1a
parsePlicState.py bugfix
2022-04-13 13:04:43 -07:00
bbracker
3465d8cd32
improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
2022-04-13 03:37:53 -07:00
bbracker
0d4ec9b3f9
fix bugs in PLIC checkpoint state parsing
2022-04-13 01:59:21 -07:00
bbracker
1bb5e1f35b
whoops fix address for PLIC int enables in checkpoint generation
2022-04-13 01:36:09 -07:00
bbracker
54c5f7f607
deprecate remove_dup.awk in favor of expanding parseGDBtoTrace.py to internally remove duplicates; this way the instruction counts in traps.txt are hopefully now in sync with the line numbers of all.txt
2022-04-07 19:43:22 -07:00
bbracker
008089b470
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-07 08:37:44 -07:00
bbracker
0a0956fad0
fix parseQEMUtoGDB.py to pass on interrupt messages correctly
2022-04-07 04:47:15 -07:00
kaveh Pezeshki
49aae4b2e9
using -S for busybox objdump to provide source code snippets
2022-04-06 23:06:49 +00:00
bbracker
0f394ba18b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-06 07:50:57 -07:00
bbracker
0a8ce0593a
filter traps list down to just interrupts
2022-04-06 07:49:44 -07:00
bbracker
ea0471dcc7
change RAM size in genInitMem.sh
2022-04-06 07:49:04 -07:00
David Harris
23da303ad3
Added bootmem source ccode
2022-04-05 23:22:53 +00:00
David Harris
c6960ede37
Changed Linux disassembly to -S to preserve source code lines
2022-04-01 16:49:13 +00:00
bbracker
a5c32898a0
checkpointSweep is bash-specific, so add shebang to make it so
2022-03-28 13:40:50 -07:00
bbracker
501dc7cd68
fix genCheckpoint.sh binary memory dump
2022-03-27 20:54:59 -07:00
bbracker
9b5bbd29b4
change genCheckpoint.sh to only log 128MB of RAM
2022-03-27 19:16:39 -07:00
bbracker
4e1b50e50c
fix parseGDBtoTrace.py to expect the CSRs that QEMU actually prints out
2022-03-27 19:05:44 -07:00
bbracker
800bc85519
refactored buildroot configuration
2022-03-27 15:13:03 -07:00
bbracker
0eeb6cc5b5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-27 15:11:42 -07:00
bbracker
8d5c231a13
change devicetree to expect only 128MB of RAM
2022-03-27 15:11:36 -07:00
bbracker
6f6663cd67
fix multiple-context PLIC checkpoint generation
2022-03-25 01:02:22 +00:00
bbracker
4b376e2834
1st attempt at multiple channel PLIC
2022-03-24 17:08:10 -07:00
