67 Commits

Author	SHA1	Message	Date
bbracker	c8c87bd0d8	merge testbench	2021-04-08 14:28:01 -04:00
bbracker	ce7b2314ef	Yee hoo first draft of PLIC plus self-checking tests	2021-04-04 06:40:53 -04:00
James E. Stine	9026357350	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
ushakya22	ba01d57767	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
Jarred Allen	6cda818f09	Merge branch 'cache2' into cache ... Conflicts: wally-pipelined/testbench/testbench-imperas.sv	2021-03-30 13:32:33 -04:00
Jarred Allen	85164c7a87	Merge branch 'main' into cache ... Conflicts: wally-pipelined/regression/wave-dos/ahb-waves.do wally-pipelined/src/ifu/ifu.sv wally-pipelined/testbench/testbench-busybear.sv wally-pipelined/testbench/testbench-imperas.sv	2021-03-30 12:55:01 -04:00
Jarred Allen	c8a88757ab	Fix error when reading an instruction that crosses a line boundary	2021-03-25 18:47:23 -04:00
ShreyaSanghai	da4086db79	Removed PCW and InstrW from ifu	2021-03-26 01:53:19 +05:30
Jarred Allen	73d4dd8c15	Begin work on compressed instructions	2021-03-25 14:43:10 -04:00
Jarred Allen	feabcf2d50	Make cache output NOP after a reset	2021-03-25 13:18:30 -04:00
Jarred Allen	e8e4e1bee2	rv64i linear control flow now working	2021-03-25 13:02:26 -04:00
Jarred Allen	c16605a105	Remove deleted signal from waves	2021-03-23 14:17:17 -04:00
Jarred Allen	639a718312	Fix conflicts in ahb-waves that snuck through manual merging	2021-03-20 17:16:50 -04:00
Jarred Allen	50c961bbe4	Merge changes from main	2021-03-18 18:58:10 -04:00
Jarred Allen	bf2fbf49ee	Add icache's read request to ahb wavs	2021-03-18 18:52:03 -04:00
bbracker	df51d9908d	AHB bugfixes and sim waveview refactoring	2021-03-18 18:25:12 -04:00
bbracker	11ba96f2e3	maybe AHB works now	2021-03-18 17:47:00 -04:00