Github_Repos/cvw
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10,013 Commits 4 Branches 2 Tags 53 MiB
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158 Commits

Author SHA1 Message Date
Ross Thompson
5d4051d1c2 Constraints for fpga are still wrong. 2021-12-02 14:23:21 -06:00
Ross Thompson
2cfbdb1c47 Added tcl commands to build the implementation. 2021-12-02 10:17:30 -06:00
Ross Thompson
6a228ade04 Got fpga synthesis running from scripts. 2021-12-01 16:59:04 -06:00
Ross Thompson
7f52d86980 Added make clean to fpga IP generator. 2021-11-29 18:42:28 -06:00
Ross Thompson
1117b90f40 Created Makefile to manage IP generation. 2021-11-29 18:33:58 -06:00
Ross Thompson
84116a756e Added final IP generator script (proc_sys_reset). 2021-11-29 17:43:47 -06:00
Ross Thompson
ce91732856 Added ddr4 generator script. 2021-11-29 15:56:57 -06:00
Ross Thompson
9a0bf54840 Created tcl scripts to build 2 of the 4 xilinx IP. 2021-11-29 11:26:08 -06:00