Ross Thompson
ddbc659d7b
Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do.
2021-08-19 10:33:11 -05:00
Ross Thompson
65870877c3
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-08-17 16:06:54 -05:00
Ross Thompson
91b51c698e
Minor changes to dcache.
2021-08-17 15:22:10 -05:00
Katherine Parry
c8847b27e8
all conversions go through the execute stage result mux
2021-08-16 13:06:09 -04:00
Ross Thompson
a70d51f4c9
Modified the hptw's simulation error message so that synthesis does not attempt to include this statement.
2021-08-16 10:02:29 -05:00
Ross Thompson
36761d9155
Fixed syntax errors in some floating point modules. This came up in
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Xilinx synthesis.
2021-08-15 16:48:49 -05:00
Ross Thompson
6c57002d0e
Added logic to linux test bench to not stop simulation on csr write faults.
2021-08-15 11:13:32 -05:00
Ross Thompson
af2c6fd6ff
Updated linux-wave.do to have cursors at the timer interrupt problem.
2021-08-13 17:29:37 -05:00
Ross Thompson
766c829d31
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-08-13 17:23:04 -05:00
Ross Thompson
55fda4de62
Switched ExceptionM to dcache to be just exceptions.
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Added test bench logic to hold forces until the W stage is unstalled.
2021-08-13 15:53:50 -05:00
Ross Thompson
32db21659f
Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token.
2021-08-13 14:53:43 -05:00
Ross Thompson
e141a00934
Cleaned up the linux testbench by removing old code and signals.
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Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
2021-08-13 14:39:05 -05:00
Katherine Parry
aedd71d570
move some FPU select muxs to execute stage
2021-08-13 14:41:22 -04:00
Ross Thompson
4f5007a9ea
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-08-12 18:05:48 -05:00
Ross Thompson
6a6d5e9b15
Added documentation about how the dcache and ptw interact.
2021-08-12 18:05:36 -05:00
Ross Thompson
814fd80b0f
Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate.
2021-08-12 13:36:33 -05:00
Ross Thompson
9ff9c4dff9
Minor cleanup of the linux test bench.
2021-08-12 11:14:55 -05:00
Abe
44c7494a30
Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation.
2021-08-12 05:23:04 -04:00
Ross Thompson
565c01709d
Removed unused states from dcache fsm.
2021-08-11 17:06:09 -05:00
Ross Thompson
2be625d8b9
Modified invalid plic reads to return 0 rather than deadbeaf.
2021-08-11 16:56:22 -05:00
Ross Thompson
4b25fed6d8
Simplified Dcache by sharing the read data mux with the victim selection mux.
2021-08-11 16:55:55 -05:00
Ross Thompson
22f274c51e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-08-10 13:36:29 -05:00
Ross Thompson
67c1028862
Dcache and LSU clean up.
2021-08-10 13:36:21 -05:00
Katherine Parry
e00f181bcf
LZA added to FMA and attemting a merged FMA and adder in synthesis
2021-08-10 13:57:16 -04:00
Ross Thompson
cce0571925
Fixed another bug with the atomic instrucitons implemention in the dcache.
2021-08-08 22:50:31 -05:00
Ross Thompson
d3be04b7de
Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the
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cache's SRAM would occur. Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
2021-08-08 11:42:10 -05:00
Ross Thompson
fc7016eea6
Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.
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Fixed logic for trace update in the M and W stages. The M stage should not update if there
is an instruction fault.
2021-08-08 00:28:18 -05:00
Ross Thompson
aa9a5d879b
Finally past the CLINT issues.
2021-08-06 16:41:34 -05:00
Ross Thompson
0bfbcef8ab
Now past the CLINT issues.
2021-08-06 16:16:39 -05:00
Ross Thompson
9be10cdc8b
Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.
2021-08-06 16:06:50 -05:00
Ross Thompson
c749d08542
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
Ross Thompson
3582be4dbb
Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.
2021-08-05 16:49:03 -05:00
Ross Thompson
37ba6b19e5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-30 17:57:13 -05:00
Ross Thompson
f808b29065
Added some comments to linux testbench.
2021-07-30 17:57:03 -05:00
Ross Thompson
e166cc84ee
Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files.
2021-07-30 14:24:50 -05:00
Ross Thompson
74fba4bb06
Moved the test bench modules to a common directory.
2021-07-30 14:16:14 -05:00
Ross Thompson
7b9e53fbe5
Removed 1 cycle delay on store miss.
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Changed some logic to partially support atomics.
2021-07-30 14:00:51 -05:00
Ross Thompson
d8878581f4
Created new linux test bench and parsing scripts.
2021-07-29 20:26:50 -05:00
Katherine Parry
d60e394ef9
all fpu units use the unpacking unit
2021-07-28 23:49:21 -04:00
Ross Thompson
915d8136e5
Fixed bug which caused stores to take an extra clock cycle.
2021-07-26 12:22:53 -05:00
Ross Thompson
79ebc53977
Fixed bug with the compressed immediate generation. Several formats should zero extend.
2021-07-26 11:55:31 -05:00
Ross Thompson
ef55b30e99
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-26 11:55:00 -05:00
Ross Thompson
60177b92a6
Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation.
2021-07-25 23:14:28 -05:00
Katherine Parry
30ac22edff
fixed some fpu lint errors
2021-07-24 16:41:12 -04:00
Katherine Parry
6c4aa624a5
fpu cleanup
2021-07-24 15:00:56 -04:00
Katherine Parry
ef28679721
fpu cleanup
2021-07-24 14:59:57 -04:00
Kip Macsai-Goren
3008111bcd
added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet
2021-07-23 16:02:42 -04:00
Kip Macsai-Goren
381a93b45b
added sfence to legal instructions, zeroed out rom file to populate for tests
2021-07-23 15:55:08 -04:00
Kip Macsai-Goren
221b8097d6
uppdated makefile to not simulate pmp/pma tests with ovpsim
2021-07-23 15:29:03 -04:00
Kip Macsai-Goren
63f8a97939
fixed write pmp csr test, added physical exe test, fixed instr fault return problem, general light cleanup
2021-07-23 15:27:54 -04:00
