Ross Thompson
dfd07a57fd
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
Ross Thompson
9d23b0e6d6
Reorganized the configs.
2022-10-09 16:46:48 -05:00
David Harris
37f0b52520
Fixed address decoder hanging buildroot
2022-08-26 22:01:25 -07:00
David Harris
2b241f8bbd
Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding
2022-08-26 21:18:18 -07:00
David Harris
812158aeee
Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
2022-08-26 20:26:12 -07:00
David Harris
95dd50a567
Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
2022-08-26 20:12:03 -07:00
Ross Thompson
3b612d6201
Possible fixes for earily messup of rv32ic and rv64ic configs.
2022-08-25 14:42:08 -05:00
Ross Thompson
e605ef57dc
BROKEN. Don't use this commit.
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Issue running cacheless with bus.
2022-08-25 11:02:46 -05:00
Ross Thompson
769af32f2a
Renamed RAM to UNCORE_RAM.
2022-08-24 18:09:07 -05:00
Ross Thompson
51adf6cba9
Modified the lsu/ifu memory configurations.
2022-08-24 12:35:15 -05:00
Ross Thompson
69d520a7eb
Removed replay from the config files.
2022-07-24 00:34:11 -05:00
slmnemo
528869ef14
Removed references to initialization files
2022-06-23 16:50:27 -07:00
DTowersM
4e5d7ec3d6
changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
2022-06-10 00:37:53 +00:00
David Harris
8066ba45e8
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
Kip Macsai-Goren
3d1e1202f3
set WFI timeout to after 16 bits of counting for all configs
2022-04-28 18:14:08 +00:00
Shreya Sanghai
c3164f0ce1
added bpred size to wally config
2022-04-18 04:21:03 +00:00
David Harris
2436534687
First implementation of WFI timeout wait
2022-04-17 17:20:35 +00:00
Katherine Parry
20885f4dea
generating all testfloat vectors
2022-04-04 17:17:12 +00:00
Ross Thompson
e802deb4d6
Can now support the following memory and bus configurations.
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1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
2022-03-11 15:18:56 -06:00
bbracker
6caa97bb26
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
2022-02-22 03:46:08 +00:00
Ross Thompson
6cd9d84e7f
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
308cc34d6f
Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
2022-02-04 23:49:07 -06:00
David Harris
9e0055cbb9
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
David Harris
bdf1a8ba73
changed DMEM and IMEM configurations to support BUS/TIM/CACHE
2022-02-03 00:41:09 +00:00
David Harris
172a02551b
Removed Busybear and Buildroot Configuration
2022-02-02 20:32:22 +00:00
David Harris
761dae72fe
Config file & wally-riscv-arch-test cleanup
2022-02-02 16:35:52 +00:00
David Harris
c6adb7b6b1
Updated configs to fix GPIO address to match FU540
2022-01-26 18:16:34 +00:00
Ross Thompson
5726b5b640
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
9f7e3f147b
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
Ross Thompson
ecd3912900
Set rv32ic to not use icache.
2022-01-12 14:10:09 -06:00
Ross Thompson
888a60d8d6
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
