Katherine Parry
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67c99d3d1a
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added input enables and improved forwarding
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2022-07-21 01:20:06 +00:00 |
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Daniel Torres
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d33d0d22bd
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commented out embench 2.0 tests
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2022-07-19 13:36:18 -07:00 |
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Katherine Parry
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4c2afbbc4f
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moved Se into execute stage
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2022-07-19 01:10:10 +00:00 |
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Katherine Parry
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e599f82b29
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moved Ss to execute stage
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2022-07-18 20:48:56 +00:00 |
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Katherine Parry
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921debf930
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removed underflow from inexactct calculation
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2022-07-18 17:51:18 +00:00 |
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Katherine Parry
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5bb1478859
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renamed signals in ocde to match book
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2022-07-18 17:31:17 +00:00 |
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Katherine Parry
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e251022269
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merged floating-point radix-2 divider with radix-4
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2022-07-15 20:16:59 +00:00 |
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Katherine Parry
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b069cfbec2
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fixed error in divsqrt
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2022-07-14 18:16:00 +00:00 |
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Katherine Parry
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77ea4e47cb
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removed minus 1 case in rounding
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2022-07-13 15:01:38 -07:00 |
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Katherine Parry
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e05b2a07d2
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removed warnings and took a mux out of the critical path
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2022-07-12 18:32:17 -07:00 |
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Katherine Parry
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2ada8a8bc1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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Katherine Parry
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7815b81716
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-11 18:30:29 -07:00 |
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Katherine Parry
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b728e5054d
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variable interations implemented in radix-4 divider
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2022-07-11 18:30:21 -07:00 |
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DTowersM
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191c7a2ee3
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added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
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2022-07-11 21:13:09 +00:00 |
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Katherine Parry
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ca4fe08fd9
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
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Katherine Parry
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cd53ae67d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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Katherine Parry
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3476579e02
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-08 12:30:50 -07:00 |
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Katherine Parry
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9ef45f36fd
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renamed signals in cvt and prostproc
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2022-07-08 12:30:43 -07:00 |
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David Harris
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d10ad0e883
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Removed testbench code that ignores mismatch on zero signatures
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2022-07-08 09:17:31 +00:00 |
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DTowersM
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5a68ff9afb
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
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2022-07-07 23:11:35 +00:00 |
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DTowersM
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d55833e4f3
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new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory
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2022-07-07 23:11:02 +00:00 |
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Katherine Parry
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41c16be012
|
srt divider merged into fpu
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2022-07-07 16:01:33 -07:00 |
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David Harris
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2f342c430e
|
fixing port errors
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2022-07-07 21:57:10 +00:00 |
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Katherine Parry
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0b40f38f02
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added load and store test
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2022-07-07 21:48:51 +00:00 |
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DTowersM
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47a990d9f1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
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2022-07-06 23:44:27 +00:00 |
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DTowersM
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1e8ccf3449
|
added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu
|
2022-07-06 23:43:57 +00:00 |
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David Harris
|
dab87811e9
|
Removed sig4 spurious message from testbench
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2022-07-05 03:27:14 +00:00 |
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Katherine Parry
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010a05f583
|
added missing files
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2022-07-03 21:40:47 -07:00 |
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Katherine Parry
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1b4584e825
|
Renaming signals to match chapter
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2022-07-03 12:26:22 -07:00 |
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Daniel Torres
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a384a6465b
|
reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished
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2022-06-29 12:32:30 -07:00 |
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Daniel Torres
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50b9b4557c
|
added changes to testbench, tests and riscof for additional riscof compatability
|
2022-06-29 12:23:40 -07:00 |
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slmnemo
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448c9fdbb9
|
Add CLINT tests from book
|
2022-06-27 20:09:58 -07:00 |
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Katherine Parry
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f25bb4a384
|
radix-4 early termination working for special cases - not working completely
|
2022-06-27 20:43:55 +00:00 |
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Katherine Parry
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06f7f9b147
|
fixed commented out error and removed killprod from result selection
|
2022-06-25 01:42:23 +00:00 |
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Katherine Parry
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d058ec6329
|
added denormal input handeling - radix 4
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2022-06-24 19:41:40 +00:00 |
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Katherine Parry
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b54d84195f
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added radix-4 0/d handling
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2022-06-23 22:36:19 +00:00 |
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Katherine Parry
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5133b08161
|
generate qsel4 in verilog
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2022-06-23 21:38:04 +00:00 |
|
Katherine Parry
|
49067792dc
|
fixt lint error
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2022-06-23 16:11:50 +00:00 |
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Katherine Parry
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4a6dee5926
|
Testfloat running division - not passing
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2022-06-23 00:07:34 +00:00 |
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David Harris
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8537b883d1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-21 22:45:28 +00:00 |
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slmnemo
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2b2760f5bd
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-21 02:16:26 -07:00 |
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slmnemo
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2b2ddbcc5e
|
Added rudimentary GPIO test according to testplans in chapter 15
|
2022-06-21 02:16:21 -07:00 |
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Katherine Parry
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254ebf478e
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
|
Daniel Torres
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d077199608
|
embench and testbench now support running both O2 and Os build variations without overwriting one another
|
2022-06-17 21:15:42 -07:00 |
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Daniel Torres
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1ef5ed8005
|
arch tests now run on spike and sail and compare signatures during build
|
2022-06-17 20:53:15 -07:00 |
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Daniel Torres
|
dcdd3702c3
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
3a5c02b44a
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
|
David Harris
|
ecd733942a
|
Removed testbench.sv.bak
|
2022-06-14 22:04:38 +00:00 |
|
DTowersM
|
919c1818a8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 23:34:35 +00:00 |
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DTowersM
|
1f4d56ba32
|
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
|
2022-06-13 23:23:57 +00:00 |
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