David Harris
cbef88ec10
Lab 3 file cleanup
2022-02-08 10:26:37 +00:00
David Harris
50b44b4416
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-07 14:43:31 +00:00
David Harris
9b55848ffc
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
bbracker
74ef58e20e
remove rv32e from regression because it is broken; goes with previous commit
2022-02-05 23:05:21 +00:00
David Harris
0f7b8017d1
Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
2022-02-05 05:35:51 +00:00
David Harris
a9d2386010
Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts
2022-02-05 05:28:40 +00:00
David Harris
66b4834ef5
Modified wally-pipelined-batch.do to handle buildroot
2022-02-05 05:07:07 +00:00
David Harris
72bc64ef28
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
2022-02-05 04:16:18 +00:00
David Harris
2c67f32b97
RV32e tests
2022-02-04 14:30:36 +00:00
David Harris
ef5af9b5fd
renamed configs
2022-02-03 23:36:41 +00:00
David Harris
a6708ed887
cache cleanup
2022-02-03 15:36:11 +00:00
Ross Thompson
b642a19e12
Merge branch 'makefiles' into main
2022-02-03 08:33:50 -06:00
Ross Thompson
c34907c95b
Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the
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regression directory. Makefile calls the submakefiles for generating elf files.
The second makefile-memfiles generates the memfiles, addr, and label files.
2022-02-03 08:32:48 -06:00
Ross Thompson
9336682749
Manged to get all the tests compiled and converted to memfiles using new makefiles.
2022-02-03 00:00:15 -06:00
Ross Thompson
06c5a825c4
Quick patch to regression-wally to "fix" rv32ic.
2022-02-02 19:24:24 -06:00
Ross Thompson
5c640b6582
broken makefiles.
2022-02-02 19:15:11 -06:00
Ross Thompson
943dff106e
Broken makefiles.
2022-02-02 19:14:42 -06:00
David Harris
38bbe23d14
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
Ross Thompson
98990a294c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-02 11:41:54 -06:00
David Harris
4ba37d5cc0
Config file & wally-riscv-arch-test cleanup
2022-02-02 16:35:52 +00:00
Ross Thompson
2d827bf8c0
Added helpful signals to wavefile.
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Makefile for tests now creates the function address to name mapping files.
The function name and test name are included in the wave file.
2022-02-02 10:15:54 -06:00
Ross Thompson
143bdaa288
Modified makefiles to generate function address to name mappings for modelsim.
2022-02-01 18:25:03 -06:00
Ross Thompson
f055441ecf
Improved function_radix to not printout warnings when no valid function is found.
2022-02-01 18:03:09 -06:00
Ross Thompson
5407b72af9
Setup the main regression test to be able to handle coremark.
2022-02-01 17:00:11 -06:00
Ross Thompson
c9a163b8fd
Repaired linux-wave.do
2022-01-31 12:54:18 -06:00
Ross Thompson
4422e2f91c
Repaired wavefile and fixed modelsim warning.
2022-01-31 12:34:17 -06:00
Ross Thompson
2e00186eea
Updated wave.do to match the ifu/lsu changes.
2022-01-28 14:37:15 -06:00
Ross Thompson
862bf2faae
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
284d671da3
Increased number of concurrent tests.
2022-01-27 08:45:25 -06:00
Ross Thompson
3ebcd35a8c
Added colors to regression script to make it easy to pick out success from fail.
2022-01-26 22:40:32 -06:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
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2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
39d318fb2a
Fixed path to riscvOVPsimPlus
2022-01-21 00:12:14 +00:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
cea09aab98
Removed imperas tests from makefile for now
2022-01-20 14:51:56 +00:00
David Harris
fc932ef0ff
Added top-level make clean
2022-01-20 14:17:26 +00:00
David Harris
ebf9f5d526
riscvsingle reparittioned to match Ch4
2022-01-17 16:57:32 +00:00
David Harris
55b4423329
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
325724f556
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
6febce0001
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
fd13272d4c
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
Ross Thompson
3bec276862
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
Ross Thompson
a973681a90
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
85b5dc08a8
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
786a772444
Improve wavefile by adding performance counters.
2022-01-12 10:53:29 -06:00
David Harris
3a2b459439
Merged coremark changes
2022-01-10 05:09:28 +00:00
David Harris
39d5570d2c
Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
2022-01-10 05:04:13 +00:00
Ross Thompson
73c488914f
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
04ea93aa27
Added performance counters to wavefile.
2022-01-09 22:42:14 -06:00
Ross Thompson
ae927e2bc6
Fixed wavefile.
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Converted coremark to use elf2hex.
2022-01-09 22:03:10 -06:00
David Harris
0212260eef
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-09 14:39:33 +00:00
Ross Thompson
509a0cd3f8
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
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only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
54d852f6ae
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00
David Harris
cb68548b88
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 23:04:33 +00:00
David Harris
fc4db84bbc
Makefile make allclean
2022-01-06 23:04:30 +00:00
Katherine Parry
b3ebce0365
some FPU test fixes
2022-01-06 23:03:20 +00:00
David Harris
31067c8e7d
Restored many of the arch32f and arch64d that had been failing because of memfile issues
2022-01-05 22:23:46 +00:00
David Harris
30c1ab5213
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-05 22:10:33 +00:00
David Harris
355efda9bc
Replaced exe2memfile with SiFive elf2hex
2022-01-05 22:10:26 +00:00
Ross Thompson
75788dd9c2
Changes to wave file.
2022-01-05 14:16:59 -06:00
David Harris
c1d6550ccb
Removed generate statements
2022-01-05 14:35:25 +00:00
Ross Thompson
06168e67e4
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
David Harris
08e6a10480
Removed imperas mmu tests; using wallypriv instead
2022-01-04 23:14:53 +00:00
David Harris
1f07470477
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
