Ross Thompson 5407b72af9 Setup the main regression test to be able to handle coremark.		2022-02-01 17:00:11 -06:00
..
slack-notifier
wave-dos	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
buildrootBugFinder.py
fpga-wave.do	Updated wave.do to match the ifu/lsu changes.	2022-01-28 14:37:15 -06:00
lint-wally
linux-wave.do	Repaired linux-wave.do	2022-01-31 12:54:18 -06:00
make-tests.sh
Makefile	Fixed path to riscvOVPsimPlus	2022-01-21 00:12:14 +00:00
regression-wally	Increased number of concurrent tests.	2022-01-27 08:45:25 -06:00
sim-buildroot
sim-buildroot-batch
sim-coremark-batch
sim-fp64
sim-fp64-batch
sim-wally	LSU Cleanup	2022-01-15 01:11:17 +00:00
sim-wally-batch	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
wally-buildroot-batch.do
wally-buildroot.do
wally-coremark.do
wally-fp64-batch.do
wally-fp64.do
wally-harvard.do	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
wally-pipelined-batch.do
wally-pipelined-fpga.do
wally-pipelined-tim-batch.do	Added tim only test to regression-wally. Minor cleanup to ifu.	2022-01-14 11:13:06 -06:00
wally-pipelined-tim.do	Added tim only test to regression-wally. Minor cleanup to ifu.	2022-01-14 11:13:06 -06:00
wally-pipelined.do
wave-all.do	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
wave-coremark.do	Updated wave.do to match the ifu/lsu changes.	2022-01-28 14:37:15 -06:00
wave.do	Setup the main regression test to be able to handle coremark.	2022-02-01 17:00:11 -06:00