9 Commits

Author	SHA1	Message	Date
David Harris	8372bc86a7	Removing unused signals	2022-05-12 14:36:15 +00:00
David Harris	4fbf78e049	clean up sram1p1rw; still doesn't work on Modelsim 2022.1	2022-05-03 08:31:54 -07:00
David Harris	bc132c3e20	sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera	2022-05-03 03:50:41 -07:00
David Harris	3f2ec0499f	Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.	2022-05-03 03:45:41 -07:00
Ross Thompson	b2a77da96b	Changed sram1p1rw to have the same type of bytewrite enables as bram.	2022-03-30 11:38:25 -05:00
Ross Thompson	bdfca503fa	Name cleanup.	2022-03-10 18:44:50 -06:00
Ross Thompson	d77adbd673	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	d5f524a15e	Added byte write enables to cache SRAMs.	2022-03-10 15:48:31 -06:00
Ross Thompson	e00d404154	More cache cleanup.	2022-02-10 10:43:37 -06:00