57 Commits

Author	SHA1	Message	Date
Katherine Parry	4ea56ac68b	some fpu lint warnings fixed - still working on it	2021-10-11 18:32:03 -07:00
bbracker	8eff03bf1a	simplify flopenrc's that didn't actually need to be flopenrc's	2021-10-10 12:25:05 -07:00
Katherine Parry	44b023ace1	FMA matches diagram and lint warnings fixed	2021-10-09 17:38:10 -07:00
James E. Stine	b90d7b8083	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
Katherine Parry	7607adc951	FMA cleanup	2021-08-28 10:53:35 -04:00
Katherine Parry	facd4062d0	all conversions go through the execute stage result mux	2021-08-16 13:06:09 -04:00
Katherine Parry	567260751a	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
Katherine Parry	21555c392f	LZA added to FMA and attemting a merged FMA and adder in synthesis	2021-08-10 13:57:16 -04:00
Katherine Parry	d8ca70fc45	all fpu units use the unpacking unit	2021-07-28 23:49:21 -04:00
Katherine Parry	67ab0b165c	fpu cleanup	2021-07-24 14:59:57 -04:00
David Harris	c04f40d6e5	Move Z=0 mux out of unpacker.	2021-07-22 14:22:28 -04:00
David Harris	625d925369	Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken.	2021-07-22 14:18:27 -04:00
David Harris	2f23ca2b77	Removed Assumed1 from FPU interface	2021-07-22 13:04:47 -04:00
David Harris	926ffc8a15	Simplified interface to fclassify and fsgn (fixed)	2021-07-22 12:33:38 -04:00
David Harris	ae29eaa98d	Simplified interface to fclassify and fsgn	2021-07-22 12:30:46 -04:00
Katherine Parry	59f79722ab	FDIV and FSQRT work	2021-07-21 14:08:14 -04:00
James E. Stine	b36d6fe1be	slight mod to fpdiv - still bug in batch vs. non-batch	2021-07-20 01:47:46 -04:00
Katherine Parry	3527620c0b	fdivsqrt inegrated, but not completley working	2021-07-18 14:03:37 -04:00
Katherine Parry	701ea38964	Fixed lint warning	2021-07-14 21:24:48 -04:00
Katherine Parry	f8b76082e4	fpu unpacking unit created	2021-07-14 17:56:49 -04:00
James E. Stine	45a6e96673	mod 2 of fpdivsqrt update	2021-07-13 16:59:17 -04:00
Katherine Parry	acdd2e4504	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
Katherine Parry	a4bd128978	fcvt.sv cleanup	2021-07-11 21:30:01 -04:00
Katherine Parry	0cc07fda1b	Almost all convert instructions pass Imperas tests	2021-07-11 18:06:33 -04:00
David Harris	e65fb5bb35	Added F_SUPPORTED flag to disable floating point unit when not in MISA	2021-07-05 10:30:46 -04:00
David Harris	b8b7fab02b	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
Katherine Parry	3f61e313d2	FPU update	2021-07-02 12:40:58 -04:00
Katherine Parry	6216bd7172	FPU control signals changed and FMA works	2021-06-28 18:53:58 -04:00
Katherine Parry	bc8d660bc5	FPU forwarding reworked pt.1	2021-06-24 18:39:18 -04:00
Katherine Parry	44af47608c	fpu clean-up	2021-06-23 16:42:40 -04:00
Katherine Parry	9eb6eb40bf	rv64f FLW passes imperas tests	2021-06-22 16:36:16 -04:00
Katherine Parry	26bad083ad	all rv64f instructions except convert, divide, square root, and FLD pass	2021-06-20 20:24:09 -04:00
Katherine Parry	920ff984ca	Updated FMA	2021-06-14 13:42:53 -04:00
Katherine Parry	b55798f09b	lint is clean	2021-06-07 14:22:54 -04:00
Katherine Parry	e4db6ea6f5	fixed lint warnings for fpu and lzd	2021-06-05 12:06:33 -04:00
Katherine Parry	19116ed889	Double-precision FMA instructions	2021-06-04 14:00:11 -04:00
Ross Thompson	db2a38c300	Fixed a few lint errors, ... clock gater was wrong, missing signal definitions in branch predictor.	2021-06-02 09:33:24 -05:00
James E. Stine	2c140679e3	Minor cosmetic update to fpu.sv	2021-06-01 15:45:32 -04:00
Ross Thompson	8e330367ac	added clock gater to floating point divider to speed up simulation time.	2021-06-01 13:46:21 -05:00
Katherine Parry	0646e08609	classify unit created and passes imperas tests	2021-05-27 18:53:55 -04:00
Katherine Parry	65eca433b6	All compare instructions pass imperas tests	2021-05-27 15:23:28 -04:00
Katherine Parry	bd05de0dbb	FADD and FSUB imperas tests pass	2021-05-26 12:33:33 -04:00
Katherine Parry	3869a73a9c	renamed top level FPU wires	2021-05-25 20:04:34 -04:00
James E. Stine	e32e812f6a	Update FPregfile to use more compact code and better structure for ease in reading	2021-05-25 13:21:59 -05:00
Katherine Parry	03aea055fa	FMV.X.D imperas test passes	2021-05-24 14:44:30 -04:00
James E. Stine	194c32defa	Update header for FPadd	2021-05-24 08:28:16 -05:00
Katherine Parry	55f22979ca	FSD and FLD imperas tests pass	2021-05-23 18:33:14 -04:00
Katherine Parry	71e4a10efb	FMV.D.X imperas test passes	2021-05-20 22:17:59 -04:00
Katherine Parry	409438bc95	floating point infinite loop removed from imperas tests	2021-05-18 10:42:51 -04:00
Katherine Parry	3f05e31954	fpu warnings fixed/commented	2021-05-03 19:17:09 +00:00