8 Commits

Author	SHA1	Message	Date
David Harris	aef408af58	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
David Harris	72d8d34e3c	allow all size memory access in CLINT; added underscore to peripheral address symbols	2021-06-18 08:05:50 -04:00
Thomas Fleming	d281ecd067	Remove imem from testbenches	2021-04-14 20:20:34 -04:00
Domenico Ottolia	8c7e247b58	Add mcause tests to testbench	2021-03-30 17:17:59 -04:00
ushakya22	ba01d57767	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
Domenico Ottolia	fb00d0f209	Fix bugs with privileged tests	2021-03-25 14:06:05 -04:00
Domenico Ottolia	3909158619	re-organize privileged tests to be in rv64p to rv32p folders	2021-03-24 13:51:25 -04:00
Domenico Ottolia	c9d70a1778	Add privileged testbench	2021-03-16 20:28:38 -04:00