37 Commits

Author	SHA1	Message	Date
David Harris	f5e2cff45a	Cause simplification	2022-05-12 23:47:21 +00:00
David Harris	6303d4e81f	Cause simplification	2022-05-12 23:39:10 +00:00
David Harris	de51c7eeb3	Cause simplification	2022-05-12 23:33:22 +00:00
David Harris	87dadc8208	trap/csr cleanup	2022-05-12 22:26:21 +00:00
David Harris	ea0d9fd9a8	More trap/csr simplification	2022-05-12 22:06:03 +00:00
David Harris	2eb6a65fa2	More trap/csr simplification	2022-05-12 22:04:20 +00:00
David Harris	2d8ccbd4ea	More trap/csr simplification	2022-05-12 22:00:23 +00:00
David Harris	417e36bff5	More trap/csr simplification	2022-05-12 21:55:50 +00:00
David Harris	ca6b7716e2	Simplifying trap/csr interface	2022-05-12 21:50:15 +00:00
David Harris	56c154f2e7	Simplified MTVAL logic	2022-05-12 21:36:13 +00:00
David Harris	5537c33196	Formatting cleanup	2022-05-12 18:37:47 +00:00
David Harris	5acb526375	More unused signal cleanup	2022-05-12 15:21:09 +00:00
David Harris	7e764fbda1	More unused signal cleanup	2022-05-12 15:15:30 +00:00
David Harris	e2dea3bb89	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	fb725a9e0a	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	8066ba45e8	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	2792d77e4e	Fixed bug in delegated interrupts not being taken	2022-05-08 04:50:27 +00:00
David Harris	2cdd49c7d2	WFI terminates when an interrupt is pending even if interrupts are globally disabled	2022-05-08 04:30:46 +00:00
David Harris	16ad1e0cab	Fixed InstrMisalignedFaultM mtval	2022-04-24 17:31:30 +00:00
David Harris	f1ddbb169c	Improved priority order and mtval of traps to match spec	2022-04-24 17:24:45 +00:00
Kip Macsai-Goren	7bc6943527	Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)	2022-04-22 22:46:11 +00:00
David Harris	2436534687	First implementation of WFI timeout wait	2022-04-17 17:20:35 +00:00
Ross Thompson	2294cbc1c6	Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.	2022-04-07 16:56:28 -05:00
bbracker	54b9745a75	big interrupts refactor	2022-03-30 13:22:41 -07:00
David Harris	049c55769a	fpu compare simplification, minor cleanup	2022-03-29 17:11:28 +00:00
Kip Macsai-Goren	dc9635b757	fixed double multiplication on vectored interrupts	2022-03-28 19:12:31 +00:00
David Harris	aa990be959	removed csrn and all of its outputs because depricated	2022-02-15 19:59:29 +00:00
David Harris	d8170e9dd3	Mostly removed N_SUPPORTED	2022-02-15 19:50:44 +00:00
David Harris	ed8ac3d881	Just needed to recompile - all good. Now removed uretM because N-mode is depricated	2022-02-15 19:48:49 +00:00
Ross Thompson	7fedc6b878	Cleaned up the InstrMisalignedFault.	2022-01-28 13:19:24 -06:00
Ross Thompson	1bb8d36308	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
Ross Thompson	000d713cb5	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
Ross Thompson	48c036a923	Oups. My hack for DivE interrupt prevention was wrong.	2022-01-12 14:17:16 -06:00
Ross Thompson	796316495d	Hack "fix" to prevent interrupt from occuring during an integer divide. ... This is not the desired solution but will allow continued debuging of linux.	2022-01-12 14:17:16 -06:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00