Github_Repos/cvw
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5,109 Commits 5 Branches 2 Tags 53 MiB
d1afc2f14a
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90 Commits

Author SHA1 Message Date
David Harris
d1afc2f14a Fixed configuration of ram to use macro when depth is corret 2023-01-29 11:35:17 -08:00
David Harris
33143e5958 Fixed typo in ram2p1r1wbe_1024x69 and renamed for consistency 2023-01-28 18:07:33 -08:00
David Harris
1bb1fc7604 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-28 17:55:08 -08:00
James Stine
a1d892703c Modified changes as follows 
* Add docs directory for Docker including Dockerfile
* Change to synthesis script to include fpu stuff
* Add wrappers for IP (may need some cleanup but will cleanup shortly)
 2023-01-28 19:33:00 -06:00
David Harris
4b196736a5 Renamed ram2p1rw1be to match modeule name 2023-01-27 09:54:50 -08:00
Ross Thompson
b931110f2d Renamed file missed from last commit. 2023-01-25 10:17:43 -06:00
Ross Thompson
ad6f7041b4 Fixed wrong header on optgshare.sv. Somehow it still had the old MIT license. 
Renamed ram2p1rwbefix.sv to ram2p1rwbe.sv
 2023-01-25 10:14:30 -06:00
Ross Thompson
1acbdaeca6 Removed the old two port ram and replaced it with the fixed version. 
The fixed version is renamed to ram2p1r1wb.sv
 2023-01-24 17:25:16 -06:00
Ross Thompson
1170dc7250 Moved and ranamed btb to btb.sv 
Fixed btb to use the fixed port 2 sram.
 2023-01-24 17:19:51 -06:00
Ross Thompson
c5169a3e39 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
da4eec7e0e Improved comment. 2023-01-19 17:41:57 -06:00
Ross Thompson
117ff8163b ram uses always rather than always_ff due to modelsim issue. 2023-01-19 17:41:15 -06:00
David Harris
25b607566c RAM declaration cleanup: 2023-01-19 14:47:51 -08:00
David Harris
91afe5522b generic cleanup 2023-01-14 19:02:38 -08:00
David Harris
9c79078be1 generic cleanup 2023-01-14 18:56:46 -08:00
David Harris
768c1bc703 Header comments 2023-01-12 04:35:44 -08:00
Katherine Parry
77a982c977 cleaned up all FPU files except for division 2023-01-11 22:02:30 -06:00
David Harris
8c6ddcc15b changed name to CORE-V-WALLY 2023-01-11 15:15:08 -08:00
David Harris
3ea4dd4898 Changed Wally to CORE-V Wally 2023-01-11 14:03:44 -08:00
David Harris
739c2c8322 Changed MIT license to Solderpad License 2023-01-10 11:35:20 -08:00
Ross Thompson
01d4e942d0 Added more missing files. 2023-01-06 00:12:08 -06:00
Ross Thompson
872ff619e3 Fixed problems with changes to ram2p. 2022-12-29 17:13:48 -06:00
Ross Thompson
a129e27502 signal name changes in ram2p. 2022-12-27 15:07:01 -06:00
David Harris
f0ef5caf32 Memory cleanup 2022-12-20 11:22:26 -08:00
David Harris
e74d47bcb4 Renamed renamed sram to ram 2022-12-20 08:36:45 -08:00
David Harris
16f3c25cb7 sram1p1rw cleanup 2022-12-20 02:57:51 -08:00
David Harris
08234cb1c7 Remoed unused bram modules 2022-12-20 02:40:45 -08:00
David Harris
2c46f22be5 Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:55 -08:00
David Harris
54e856c4f5 Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:36 -08:00
Ross Thompson
8692ccbafb Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00
Ross Thompson
736a30afac Missing a file. Last commit will fail. 2022-11-17 17:45:41 -06:00
Ross Thompson
1a00e7bbee Changed names of cache signals. 2022-11-13 21:36:12 -06:00
David Harris
b5d2bbe7ca changed always_ff to always in sram1p1rw to fix testbench complaint 2022-09-25 19:56:40 -07:00
Ross Thompson
6a6686a34b Removed the write first sram model. 2022-09-22 16:12:08 -05:00
Ross Thompson
29087812e1 Solved the sram write first / read first issue. Works correctly with read first now. 2022-09-22 14:16:26 -05:00
Ross Thompson
cdc80c1f28 Moved other SRAMs to generic/mem. 2022-09-21 12:36:03 -05:00
Ross Thompson
427db1f55f Renamed brom1p1r to rom1p1r. 
removed used file bram2p1r1w.sv.
 2022-09-21 12:31:20 -05:00
Ross Thompson
91fcca9d17 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
Ross Thompson
b2f4d4aaa7 Added chip enables to sram. 2022-09-20 10:49:14 -05:00
David Harris
f628622ea0 Factored out aplusbeq0 unit 2022-09-07 11:36:35 -07:00
Ross Thompson
6685b0563e James found a bug in synchronizer. Was not actually back to back flip flops. 2022-09-06 15:06:54 -05:00
Ross Thompson
2aa5886769 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
559e093ab5 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
David Harris
24ce72f0a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:52:49 -07:00
Ross Thompson
72b886ec8f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:03:34 -05:00
Ross Thompson
bc0edc7bdf Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
David Harris
b9dc8d9e33 Cleanup typos 2022-08-25 04:32:19 -07:00
David Harris
fe3147806d removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
David Harris
e6077f1f16 Added ROM module and moved memories into generic/mem 2022-08-24 17:03:22 -07:00
Ross Thompson
012559169b Fixed lint errors with bram wrapper. 2022-08-24 13:19:23 -05:00