15 Commits

Author	SHA1	Message	Date
David Harris	d3ce683e06	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
naichewa	1ab7c926ea	Final Code Review	2023-11-14 13:44:59 -08:00
naichewa	5ce16dcb63	Cleanup	2023-11-09 16:52:55 -08:00
naichewa	3052a68d84	Remove old 2/4 bit logic, add comments, ... clean up unused signals	2023-11-09 16:48:11 -08:00
naichewa	b13b8feee4	updated to-do comments	2023-11-08 15:28:51 -08:00
naichewa	d67badfc60	fix hardware interlock, hold mode deassert	2023-11-08 15:20:51 -08:00
naichewa	a5837eb62c	fifo fixes and edge case testing	2023-11-07 17:59:46 -08:00
naichewa	29e42b21df	added test cases	2023-11-02 15:42:28 -07:00
naichewa	e3d8162279	harris code review 3	2023-11-01 10:14:15 -07:00
naichewa	9aa8a7af3e	comments, more test cases	2023-11-01 01:26:34 -07:00
naichewa	fefb5adb8f	code review harris	2023-10-31 12:27:41 -07:00
naichewa	2330f4ee63	hardware interlock	2023-10-30 17:00:20 -07:00
naichewa	4941fe1769	sync fifo passes	2023-10-16 22:57:02 -07:00
naichewa	aa5abfc8e8	always working after reg bit swizzle changes	2023-10-13 14:22:32 -07:00
naichewa	d5d4f9d044	transferred spi changes in ECA-authorized commit	2023-10-12 13:36:57 -07:00