15 Commits

Author	SHA1	Message	Date
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	492ec0ee78	Removed multiplier for lab 2	2021-02-17 16:06:16 -05:00
David Harris	a7dd20b388	Multiply instructions working	2021-02-17 15:29:20 -05:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	2a80bcf543	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-02 19:44:43 -05:00
David Harris	756352f129	Minor tweaks	2021-02-02 19:44:37 -05:00
Noah Boorstin	b5f474d9f5	same thing but do that right this time	2021-02-02 21:47:15 +00:00
Noah Boorstin	6dd5c42d55	change undefined syntax in extend.sv ... don't need verilator execption anymore	2021-02-02 21:39:20 +00:00
David Harris	429f48e766	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	616830a3f0	Cleaned up hazard interface	2021-02-02 13:53:13 -05:00
David Harris	229bde5953	Moved LoadStall generation to IEU	2021-02-02 13:42:23 -05:00
David Harris	bb83fda1d8	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00