David Harris
|
3249d65209
|
Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.
|
2021-10-23 06:15:26 -07:00 |
|
Ross Thompson
|
77e2b6f9a9
|
Merge branch 'main' into fpga
|
2021-10-22 16:09:16 -05:00 |
|
kipmacsaigoren
|
2a86a6717d
|
lowered number of paths to speed synth up and removed extra unnecessary report copying.
|
2021-10-22 15:25:11 -05:00 |
|
kipmacsaigoren
|
ef297067e9
|
removed reduntant definitions for FPU in MISA.
|
2021-10-22 15:18:25 -05:00 |
|
James E. Stine
|
f6e8e45901
|
Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking
|
2021-10-22 13:41:50 -05:00 |
|
Katherine Parry
|
7c7c0f538a
|
put the FMA priority encoders into their own module
|
2021-10-22 10:03:12 -07:00 |
|
James E. Stine
|
0dcca43f48
|
Get rid of lint warning - still need more testing though
|
2021-10-21 15:19:22 -05:00 |
|
James E. Stine
|
dd7dbaa382
|
Clean up some FPU and add pipelined fpdivsqrt to fpu.sv
|
2021-10-21 13:52:12 -05:00 |
|
James E. Stine
|
bafb3a983d
|
Fix fpdivsqrt lint error on CPA for convergence
|
2021-10-20 17:46:13 -05:00 |
|
Ross Thompson
|
de4ea16d32
|
Merge branch 'main' into fpga
|
2021-10-20 16:24:55 -05:00 |
|
Ross Thompson
|
fe24bc5a43
|
Added debug signals to dcache.
|
2021-10-20 15:52:05 -05:00 |
|
David Harris
|
ceaf84a3ce
|
removed .* from wallypipeliendsoc
|
2021-10-20 13:49:18 -07:00 |
|
davidharrishmc
|
3cdac72e96
|
Update README.md
|
2021-10-20 10:49:41 -07:00 |
|
kipmacsaigoren
|
e80fd40258
|
Fixed path to src and config files, added mdu timing reports
|
2021-10-20 12:41:14 -05:00 |
|
kipmacsaigoren
|
8ea17c784a
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-10-20 12:15:53 -05:00 |
|
kipmacsaigoren
|
ffacb7ab67
|
Removed historical outputs from repo
|
2021-10-20 12:15:40 -05:00 |
|
James E. Stine
|
71b48048da
|
Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
|
2021-10-20 12:00:41 -05:00 |
|
David Harris
|
47e19d4caa
|
moved coemark and testsBP to tests
|
2021-10-20 09:10:06 -07:00 |
|
David Harris
|
140c80f3a8
|
moved imperas-riscv-tests to tests
|
2021-10-20 09:07:46 -07:00 |
|
David Harris
|
23b3d7dbc1
|
Move tests into subdirectory and moved wavedrom out of project
|
2021-10-20 09:03:21 -07:00 |
|
David Harris
|
b9e3ab7e1e
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-19 14:08:24 -07:00 |
|
David Harris
|
a88af1841f
|
radix 2 SRT checkin
|
2021-10-19 14:08:16 -07:00 |
|
bbracker
|
af998e3e27
|
gitignore the addins folder because it contains external repos
|
2021-10-19 13:32:26 -07:00 |
|
James E. Stine
|
41010aa418
|
Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this
|
2021-10-19 12:09:43 -05:00 |
|
James E. Stine
|
a75abb04bd
|
Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).
|
2021-10-19 11:58:06 -05:00 |
|
Ross Thompson
|
d11136c406
|
Fixed bug with the external memory region selection.
Updated bios program to copy just 127MB to dram.
|
2021-10-19 11:23:23 -05:00 |
|
David Harris
|
3bc985d230
|
Changed some flops to settable
|
2021-10-18 17:05:29 -07:00 |
|
David Harris
|
cc2b5eeed9
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-18 16:54:08 -07:00 |
|
David Harris
|
0516ee768b
|
replaced flopenl with flopenr when clearing to 0
|
2021-10-18 16:53:18 -07:00 |
|
davidharrishmc
|
0bb1c1c23c
|
Update README.md
|
2021-10-18 16:23:22 -07:00 |
|
David Harris
|
398337951d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-18 15:44:31 -07:00 |
|
David Harris
|
00d8035836
|
Fixed multiplier and pointed arch tests to new path in addins
|
2021-10-18 15:43:59 -07:00 |
|
Ross Thompson
|
5ce58b35a6
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-10-18 17:25:48 -05:00 |
|
Ross Thompson
|
cd58a388e4
|
fixed issues with dc shell not liking modules with parameters without default values.
|
2021-10-18 17:24:15 -05:00 |
|
davidharrishmc
|
e681020d9e
|
Update README.md
|
2021-10-18 13:43:10 -07:00 |
|
davidharrishmc
|
197a8ca7e9
|
Update README.md
|
2021-10-18 13:39:40 -07:00 |
|
davidharrishmc
|
d03e42fe95
|
Update README.md
|
2021-10-18 11:17:24 -07:00 |
|
davidharrishmc
|
7a36c48ac9
|
Update README.md
|
2021-10-18 09:52:40 -07:00 |
|
James E. Stine
|
37fe5e56a8
|
Sanitization some more on mult_cs.sv
|
2021-10-18 05:24:16 -05:00 |
|
James E. Stine
|
d0ab43e4e8
|
Update some on mult_cs and delete DW02_mult.v
|
2021-10-18 05:06:49 -05:00 |
|
James E. Stine
|
de7b673e34
|
Add hacky hand-made carry/save multiplier - will improve
|
2021-10-16 10:37:29 -05:00 |
|
Katherine Parry
|
c34633804a
|
cvtfp module documented
|
2021-10-14 15:25:31 -07:00 |
|
James E. Stine
|
c5b99300e7
|
Clean up some signals - beautification onging
|
2021-10-14 17:12:00 -05:00 |
|
Kip Macsai-Goren
|
869c35ba1c
|
Fixed typo in imperas64mmu tests causing PMP tests not to run.
|
2021-10-14 13:42:24 -07:00 |
|
Skylar Litz
|
71397d5db9
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-10-13 15:38:32 -07:00 |
|
Skylar Litz
|
4ca4e13ba2
|
add StallM signal back to DivStartE control
|
2021-10-13 15:34:40 -07:00 |
|
James E. Stine
|
1dba57dce7
|
Update to fpdivsqrt to go on posedge as it should. Also an update to
individual regression test for TestFloat (still needs some tweaking)
|
2021-10-13 17:14:42 -05:00 |
|
kipmacsaigoren
|
a898204c04
|
added outputs from synth run to test mul changes
|
2021-10-13 12:38:14 -05:00 |
|
bbracker
|
bfe972a213
|
gitignore new logs folder
|
2021-10-12 10:42:13 -07:00 |
|
bbracker
|
4abc6fc915
|
change infrastructure to expect only 6.3 million from buildroot
|
2021-10-12 10:41:15 -07:00 |
|