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Author SHA1 Message Date
Ross Thompson
cd3c1032b7 Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states. 2021-12-19 13:55:57 -06:00
Ross Thompson
1126135b80 minro change. comments about needed changes in dcache. 2021-12-19 13:53:02 -06:00
Ross Thompson
4daeb6657f Merge branch 'tlb_fixes' into main 2021-12-18 12:24:17 -06:00
David Harris
27ec8ff893 Shared ALU mux input for shifts 2021-12-18 10:08:52 -08:00
David Harris
eed2765033 Factored out common parts of shifter 2021-12-18 10:01:12 -08:00
David Harris
53baf3e787 Cleaning shifter 2021-12-18 09:43:09 -08:00
David Harris
ebcffcdebd Moved W64 truncation after result mux 2021-12-18 09:27:25 -08:00
David Harris
23c6b6370f Forwarding logic factoring 2021-12-18 05:40:38 -08:00
David Harris
10dfefa8ad Simplified FWriteInt interfaces by merging into RegWrite 2021-12-18 05:36:32 -08:00
David Harris
0f319b45c1 Do File cleanups 2021-12-17 17:45:26 -08:00
Ross Thompson
ee81cfff0c Possible fix for icache deadlock interaction with hptw. 2021-12-17 14:38:25 -06:00
David Harris
d9f569afe1 Added irscv-arch-test and rsicv-isa-sim 2021-12-15 12:38:35 -08:00
David Harris
aebd746e71 Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies 2021-12-15 12:10:45 -08:00
David Harris
4e35736e90 IEU cleanup: 2021-12-15 11:38:26 -08:00
Ross Thompson
6d2a4b8354 Oups missed files in the last commit. 2021-12-15 10:25:08 -06:00
Ross Thompson
21b13fc237 Reverted 23Mhz to 10Mhz. The flash card can't work at that speed. 
added icache debugging signals.
 2021-12-15 10:24:29 -06:00
David Harris
865d5ce0b1 Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
David Harris
d7e78f8707 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-14 13:05:47 -08:00
David Harris
ecce1e62ee changed ideal memory to MEM_DTIM and MEM_ITIM 2021-12-14 13:05:32 -08:00
Ross Thompson
9886ed3028 Comments for dcache and icache refactoring. 2021-12-14 14:46:29 -06:00
David Harris
8dcf2c65f2 renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
David Harris
0e9fe6c214 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-14 11:15:58 -08:00
David Harris
2d24230093 ALU and datapath cleanup 2021-12-14 11:15:47 -08:00
Ross Thompson
997a733a97 Added patch file for the qemu modifications. 
Added instructions for building and installing qemu.
 2021-12-13 18:36:00 -06:00
Ross Thompson
e7052d1ccf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-13 18:30:14 -06:00
Ross Thompson
ca404746ec Updated .gitignore file to hide fpga outputs. 2021-12-13 18:30:10 -06:00
Ross Thompson
af9f97454d Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
Ross Thompson
30941c073a Possible fix for icache and ptw interlock deadlock issue. 2021-12-13 18:23:43 -06:00
Ross Thompson
2d662bc4be Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-13 17:16:20 -06:00
Ross Thompson
81da8b8d2a Formating changes to cache fsms. 2021-12-13 17:16:13 -06:00
Ross Thompson
4d6d72a082 Fixed some typos in the dcache ptw interaction documentation. 2021-12-13 15:47:20 -06:00
David Harris
55f3979b67 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-13 07:57:49 -08:00
David Harris
2039752740 Simplified ALU and source multiplexers pass tests 2021-12-13 07:57:38 -08:00
kwan
8f79a12cbb priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
kwan
f0e425e4ea test 2021-12-13 00:31:51 -08:00
kwan
a365e86197 priviledge .* fixed, passed local regression 2021-12-13 00:22:01 -08:00
Kevin
03274de97c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 17:53:41 -08:00
Kevin
98420cb988 dot stars conversions on the rest of the testbenches 2021-12-12 17:53:26 -08:00
Ross Thompson
051dd7d09d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:33:29 -06:00
Ross Thompson
395766219b Revert "Privilige .*s removed" 
This reverts commit 82bab8e90e.
 2021-12-12 17:31:57 -06:00
Ross Thompson
f758a53247 Revert "Priviledged .* removed" 
This reverts commit a95efea0b3.
 2021-12-12 17:31:39 -06:00
Ross Thompson
39168a201b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:21:51 -06:00
Ross Thompson
68745d40f2 Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language. 2021-12-12 17:21:44 -06:00
Ross Thompson
f2628494e3 Missed constraints file for xilinx ILA. 2021-12-12 15:06:29 -06:00
Ross Thompson
545c586186 Added proper credit to Richard Davis, the author of the original sd card reader. 2021-12-12 15:05:50 -06:00
kwan
a95efea0b3 Priviledged .* removed 2021-12-12 09:55:45 -08:00
kwan
82bab8e90e Privilige .*s removed 2021-12-12 09:54:14 -08:00
David Harris
a7e9dee77d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 05:49:31 -08:00
Kevin
1a82b50483 edited one testbench, yet to run regression 2021-12-10 20:26:20 -08:00
Ross Thompson
4cea8d1a29 Performance counters now output of coremark. 2021-12-09 14:48:17 -06:00