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Author SHA1 Message Date
Ross Thompson
e72d54ea98 More cachefsm cleanup. 2022-02-07 13:19:37 -06:00
Ross Thompson
a6a7779ec0 More cachefsm cleanup. 2022-02-07 12:30:27 -06:00
Ross Thompson
7f732eb571 More cachefsm cleanup. 2022-02-07 11:16:20 -06:00
Ross Thompson
be67c4d559 More cachefsm cleanup. 2022-02-07 11:12:28 -06:00
Ross Thompson
f1781c6bc8 More cachefsm cleanup. 2022-02-07 10:54:22 -06:00
Ross Thompson
b89ce18473 Cache cleanup. 2022-02-07 10:43:58 -06:00
Ross Thompson
6f4a321d31 More cachfsm cleanup. 2022-02-07 10:33:50 -06:00
David Harris
60c3cdad3a Reverted cache change 2022-02-07 14:47:20 +00:00
David Harris
d0c40cca7a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-07 14:43:31 +00:00
David Harris
c21eb67a07 Cache syntax cleanup 2022-02-07 14:43:24 +00:00
Ross Thompson
8bcaadda6b More cachefsm cleanup. 2022-02-06 21:50:44 -06:00
Ross Thompson
347e9228f8 started cachefsm cleanup. 2022-02-06 21:39:38 -06:00
Kip Macsai-Goren
2ef5f2612f fixed verify step to work correctly with comments. clarified copy references without simulating 2022-02-06 19:48:23 +00:00
Kip Macsai-Goren
38b75e85a0 added new tests to make and testbench 2022-02-06 19:47:22 +00:00
Kip Macsai-Goren
5377dde581 clarified csr write test 2022-02-06 19:46:29 +00:00
Kip Macsai-Goren
6e3bec9aa5 added CSR permission tests 2022-02-06 19:45:58 +00:00
Kip Macsai-Goren
04197273f6 light cleanup 2022-02-06 02:05:59 +00:00
Kip Macsai-Goren
c5b6f49b2f added comments to existing MMU tests 2022-02-06 02:05:59 +00:00
Kip Macsai-Goren
52008b122a added commenting in reference outputs that aren't simulated in spike 2022-02-06 02:05:59 +00:00
Kip Macsai-Goren
69e79ccdf3 Allowed commenting in signature files 2022-02-06 02:05:59 +00:00
David Harris
0feb624bab Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
bbracker
27dd363a85 remove sporadic tabs from tests.vh so that it is now only spaces 2022-02-05 23:07:38 +00:00
bbracker
fc2e3d1fbf remove rv32e from regression because it is broken; goes with previous commit 2022-02-05 23:05:21 +00:00
bbracker
186267e35a Remove rv32e tests from rv32i_m Makefrag so that make XLEN=32 works 2022-02-05 21:34:50 +00:00
Ross Thompson
308cc34d6f Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. 2022-02-04 23:49:07 -06:00
David Harris
0dd8c719ad Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit 2022-02-05 05:35:51 +00:00
David Harris
f7d6939d9b Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts 2022-02-05 05:28:40 +00:00
David Harris
581fbb7d13 Modified wally-pipelined-batch.do to handle buildroot 2022-02-05 05:07:07 +00:00
Ross Thompson
1766c0f5ba Removed unused ports from caches and buses. 2022-02-04 22:52:51 -06:00
Ross Thompson
dce4f8a0e5 Cleanup. 2022-02-04 22:40:51 -06:00
Ross Thompson
53551ab533 Moved the hwdata mux back into the busdp. 2022-02-04 22:39:13 -06:00
Ross Thompson
34cf77797a Merged together the two sub cache line read muxes. 
One mux was used for loads and the other for eviction.
 2022-02-04 22:30:04 -06:00
David Harris
23868a33bc Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
Ross Thompson
c846368537 Moved the sub cache line read logic to lsu/ifu. 2022-02-04 20:42:53 -06:00
Ross Thompson
f6f0539e10 Got separate module for the sub cache line read. 2022-02-04 20:23:09 -06:00
Ross Thompson
ceb2cc30b9 Second optimization of save/restore. 2022-02-04 14:35:12 -06:00
Ross Thompson
498c2b589a Optimization of cache save/restore. 2022-02-04 14:21:04 -06:00
Ross Thompson
83fdedcec6 Working first cut of the cache changes moving the replay to a save/restore. 
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
 2022-02-04 13:31:32 -06:00
David Harris
16b5fee795 RV32e tests 2022-02-04 14:30:36 +00:00
James Stine
c1b3f5b655 Update synthesis script for overwrite during copy 2022-02-03 20:29:03 -06:00
David Harris
c80bbe8970 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-04 01:56:36 +00:00
David Harris
14c1d86953 rv32e 2022-02-04 01:56:30 +00:00
James Stine
dcb5005ba4 Update to 12T for synthesis 2022-02-03 19:42:03 -06:00
James Stine
b9480a4643 Added the 12T submodule to the project. 2022-02-03 19:26:41 -06:00
David Harris
f9b1b47fc9 Synth for 500 MHz 2022-02-04 01:06:13 +00:00
David Harris
dd26e9e87e ignore .sv files in synthDC/hdl 2022-02-04 00:57:13 +00:00
David Harris
e80139cc91 Adjusted synthesis to compile rv32e on 12T library 2022-02-04 00:45:16 +00:00
David Harris
3cc20bdd0d Added E tests to repo 2022-02-03 23:42:31 +00:00
David Harris
1c049f1f67 renamed configs 2022-02-03 23:36:41 +00:00
David Harris
e490705865 E tests 2022-02-03 22:55:55 +00:00