Ross Thompson
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ca546beaf8
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We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
This is not yet tested but the system verilog does compile.
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2021-02-15 14:51:39 -06:00 |
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Ross Thompson
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935e9e59e9
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added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
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2021-02-14 15:13:55 -06:00 |
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Ross Thompson
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8486f426b7
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The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
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2021-02-14 11:06:31 -06:00 |
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David Harris
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429f48e766
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Rename ifu/dmem/ebu signals to match uarch diagram
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2021-02-02 15:09:24 -05:00 |
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David Harris
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92bf1674b4
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
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David Harris
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07af481b67
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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