154 Commits

Author	SHA1	Message	Date
Ross Thompson	ca459a5915	Removed VDWriteEnable.	2022-02-07 21:59:18 -06:00
Ross Thompson	494802b2e1	more partial cleanup of fsm and write enables.	2022-02-07 17:41:56 -06:00
Ross Thompson	23a60d9875	Progress towards simplifying the cache's write enables.	2022-02-07 17:23:09 -06:00
Ross Thompson	fcd43ea004	more cleanup.	2022-02-07 13:29:19 -06:00
Ross Thompson	e72d54ea98	More cachefsm cleanup.	2022-02-07 13:19:37 -06:00
Ross Thompson	a6a7779ec0	More cachefsm cleanup.	2022-02-07 12:30:27 -06:00
Ross Thompson	7f732eb571	More cachefsm cleanup.	2022-02-07 11:16:20 -06:00
Ross Thompson	be67c4d559	More cachefsm cleanup.	2022-02-07 11:12:28 -06:00
Ross Thompson	f1781c6bc8	More cachefsm cleanup.	2022-02-07 10:54:22 -06:00
Ross Thompson	b89ce18473	Cache cleanup.	2022-02-07 10:43:58 -06:00
Ross Thompson	6f4a321d31	More cachfsm cleanup.	2022-02-07 10:33:50 -06:00
Ross Thompson	8bcaadda6b	More cachefsm cleanup.	2022-02-06 21:50:44 -06:00
Ross Thompson	347e9228f8	started cachefsm cleanup.	2022-02-06 21:39:38 -06:00
Ross Thompson	308cc34d6f	Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.	2022-02-04 23:49:07 -06:00
Ross Thompson	1766c0f5ba	Removed unused ports from caches and buses.	2022-02-04 22:52:51 -06:00
Ross Thompson	dce4f8a0e5	Cleanup.	2022-02-04 22:40:51 -06:00
Ross Thompson	53551ab533	Moved the hwdata mux back into the busdp.	2022-02-04 22:39:13 -06:00
Ross Thompson	34cf77797a	Merged together the two sub cache line read muxes. ... One mux was used for loads and the other for eviction.	2022-02-04 22:30:04 -06:00
Ross Thompson	c846368537	Moved the sub cache line read logic to lsu/ifu.	2022-02-04 20:42:53 -06:00
Ross Thompson	f6f0539e10	Got separate module for the sub cache line read.	2022-02-04 20:23:09 -06:00
Ross Thompson	ceb2cc30b9	Second optimization of save/restore.	2022-02-04 14:35:12 -06:00
Ross Thompson	498c2b589a	Optimization of cache save/restore.	2022-02-04 14:21:04 -06:00
Ross Thompson	83fdedcec6	Working first cut of the cache changes moving the replay to a save/restore. ... The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.	2022-02-04 13:31:32 -06:00
David Harris	c3122ce214	sram1rw cleanup	2022-02-03 18:03:22 +00:00
David Harris	0e1d784b60	sram1rw cleanup	2022-02-03 17:50:23 +00:00
David Harris	eb8dd5e7d7	cachereplacementpolicy cleanup	2022-02-03 17:19:14 +00:00
David Harris	5f7326368e	cachereplacementpolicy cleanup	2022-02-03 17:18:48 +00:00
David Harris	9b6a4d1d52	cacheway cleanup	2022-02-03 16:52:22 +00:00
David Harris	7a8cc5ef21	cacheway cleanup	2022-02-03 16:33:01 +00:00
David Harris	0fbc32204c	cacheway cleanup	2022-02-03 16:07:55 +00:00
David Harris	c22f7eb11c	cacheway cleanup	2022-02-03 16:00:57 +00:00
David Harris	e92461159d	cache cleanup	2022-02-03 15:36:11 +00:00
David Harris	9e0055cbb9	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
David Harris	bdf1a8ba73	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	c12407ba6a	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	910d16b642	More cleanup of IFU.	2022-02-01 14:32:27 -06:00
Ross Thompson	dce9ee12b4	IFU and LSU now share the same busdp module.	2022-01-31 16:25:41 -06:00
Ross Thompson	a04aa283cb	partial ifu cleanup.	2022-01-31 16:08:53 -06:00
Ross Thompson	b05abc1795	cleanup.	2022-01-31 13:29:04 -06:00
Ross Thompson	d2ab17e1af	Repaired linux-wave.do	2022-01-31 12:54:18 -06:00
Ross Thompson	3475e142a5	Repaired wavefile and fixed modelsim warning.	2022-01-31 12:34:17 -06:00
Ross Thompson	1476a79ea2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-31 12:17:37 -06:00
Ross Thompson	fa8914a830	Cleanup busdp.	2022-01-31 12:17:07 -06:00
Ross Thompson	7c3d6bbdb4	Moved lsu virtual memory logic into separate module.	2022-01-31 11:56:03 -06:00
Ross Thompson	e35a8299ec	Encapsulated dtim.	2022-01-31 11:23:55 -06:00
Ross Thompson	dbe40856a2	Removed unused signals in the LSU.	2022-01-31 10:35:35 -06:00
Ross Thompson	bfbc31d184	Moved atomic logic to own module.	2022-01-31 10:28:12 -06:00
Ross Thompson	ef770fd183	Encapsulated the bus data path into a separate module.	2022-01-31 10:15:48 -06:00
David Harris	2d112698b7	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
Ross Thompson	d52c5b0393	LSU and IFU cleanup.	2022-01-28 15:26:06 -06:00