5 Commits

Author	SHA1	Message	Date
Ross Thompson	694b3fbb6f	Possible fix for critical path timing in caches.	2021-10-25 15:33:33 -05:00
Ross Thompson	ebef47b1c9	Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.	2021-10-24 21:21:49 -05:00
David Harris	8b854bb1c2	Cleaned up LINT erors	2021-10-23 06:28:49 -07:00
bbracker	986b7a8252	change sram1rw to have a small delay so that we don't have signals changing on clock edges	2021-07-19 11:30:07 -04:00
Ross Thompson	7185905f7b	Reduced icache to 1 port memory.	2021-05-03 14:47:49 -05:00