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14 Commits 4 Branches 2 Tags 52 MiB
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14 Commits

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Author SHA1 Message Date
David Harris
c6c5dcb2ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-23 10:19:28 -05:00
David Harris
b28129fcc3 Initial checkin of UART 2021-01-23 10:19:09 -05:00
Noah Boorstin
379fc6d5ca change regfile to not hold state of x0 2021-01-22 15:12:33 -05:00
David Harris
2f24249d17 testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64 2021-01-20 01:04:28 -05:00
David Harris
9679345cae testgen-ADD-SUB initial untested 2021-01-19 22:58:56 -05:00
David Harris
820312bc87 Initial testgen checkin 2021-01-19 13:09:56 -05:00
David Harris
f9ad54f18c Changed to . notation for instantiation, cleaned up dmem 2021-01-18 20:16:53 -05:00
David Harris
dacc392c95 cleanup 2021-01-18 00:42:40 -05:00
David Harris
dc4f00c975 Sped up exe2memfile.pl 2021-01-17 18:45:19 -05:00
David Harris
6e9cff45da Added exe2memfile.py 2021-01-16 15:09:06 -05:00
David Harris
cf0958c54e Added GPIO 2021-01-15 00:25:56 -05:00
David Harris
cccb47d795 Added GPIO 2021-01-15 00:19:31 -05:00
David Harris
d6a6f67b04 Initial Checkin 2021-01-14 23:37:51 -05:00
davidharrishmc
86128ee0af Initial commit 2021-01-14 20:16:47 -08:00