336 Commits

Author	SHA1	Message	Date
Kip Macsai-Goren	c6662933c4	commented out periph test from wally32 periph so rv32ic doesn't hang	2022-12-05 20:23:16 -08:00
Kip Macsai-Goren	4e2f4855e6	added passing tests to regression	2022-12-05 20:16:02 -08:00
Kip Macsai-Goren	540d6c2f41	added -01 to all WALLY tests	2022-12-05 20:16:02 -08:00
Ross Thompson	fc05e27416	Updated riscv arch test removed misaligned1.	2022-12-04 00:18:10 +00:00
Ross Thompson	350fdd944d	Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." ... This reverts commit fb221d7b64.	2022-12-04 00:01:58 +00:00
cturek	fb221d7b64	Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.	2022-12-02 21:44:29 +00:00
David Harris	db5f3c15a4	FPU divider working with execute stage stall	2022-12-02 11:11:53 -08:00
David Harris	6079a01bc8	update test list	2022-12-02 04:28:47 -08:00
David Harris	0d23ab3ec1	reorder tests	2022-12-01 16:27:33 -08:00
David Harris	3a8602523e	FPU test list	2022-12-01 10:18:36 -08:00
Ross Thompson	2f582cd91f	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-30 13:30:37 -06:00
Ross Thompson	cedb234013	Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.	2022-11-30 11:01:25 -06:00
Ross Thompson	0454eb95ad	Preparing to merge dirty and tag srams.	2022-11-30 10:40:48 -06:00
Ross Thompson	de538d1c2f	Intermediate commit. Replaced flip flop dirty bit array with sram.	2022-11-30 00:08:31 -06:00
cturek	10c2d45888	div tests in sim-wally	2022-11-30 02:32:04 +00:00
Kip Macsai-Goren	44ea8d8b22	added failing satp invalid tests to regression	2022-11-29 10:43:38 -08:00
cturek	78c2ce5649	Updated testbench/wave for fdivsqrt new start signals	2022-11-22 22:22:26 +00:00
cturek	9d30a832c3	Reoredered tests for arch32m	2022-11-09 18:42:00 +00:00
cturek	2cbe2fd70b	Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.	2022-11-06 22:08:18 +00:00
David Harris	53a88fec8f	Reorder embench tests to prevent crash	2022-11-04 15:21:51 -07:00
Ross Thompson	a59df0c77d	Created one off test to replicate the floating point forwarding hazard bug.	2022-10-22 16:29:12 -05:00
Kip Macsai-Goren	c18c181fc0	fixed endianness mstatush problem, passes make, not regression	2022-10-04 17:37:39 +00:00
David Harris	e49e99548a	Fixed testbench-fp to support all again	2022-09-21 13:19:48 -07:00
David Harris	030fb79a3c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-09-21 10:35:11 -07:00
David Harris	cb4c3ff1ce	Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest	2022-09-21 10:35:08 -07:00
Ross Thompson	ac864a6ca3	Merged together bram1p1rw with sram1p1rw as sram1p1rw. ... Fixed a major issue with the real SRAM implemenation.	2022-09-21 12:20:00 -05:00
David Harris	87cde2c427	make QmM size b+1 indpenedent of radix	2022-09-20 03:25:09 -07:00
David Harris	8e90862dad	Removed EarlyTermShift from fdiv	2022-09-19 08:44:23 -07:00
David Harris	498c053aab	FP testbench	2022-09-18 21:27:21 -07:00
David Harris	f38bb5b32e	Divide testfloat starts with half-precision tests	2022-09-18 06:46:47 -07:00
Kip Macsai-Goren	cc7d1c8ef9	Created initial endianness tests	2022-09-16 01:06:26 +00:00
Ross Thompson	c7d3580637	Renamed signals in the LSU.	2022-09-13 11:47:39 -05:00
David Harris	c730ddf74a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-09-07 11:11:39 -07:00
David Harris	7a29f9c95b	Running 16-bit square root cases first in testfloat	2022-09-07 11:11:35 -07:00
Ross Thompson	0615798467	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-09-07 12:26:50 -05:00
David Harris	ce6e153b15	Run 16-bit fsqrt tests first	2022-09-07 10:26:09 -07:00
Ross Thompson	3571fb18c2	Modified regression tests to add some ahb configurations.	2022-09-07 12:03:58 -05:00
DTowersM	48a1abf06f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-08-31 00:18:04 +00:00
DTowersM	bdeb5c6509	fixed qrduino keyerror in embench test	2022-08-31 00:17:58 +00:00
David Harris	e1760dde55	Fixed checking termination in testfloat testbench	2022-08-30 10:55:21 -07:00
David Harris	2788022c22	renamed srt to fdivsqrt	2022-08-29 04:04:05 -07:00
David Harris	03e731b3ff	Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM	2022-08-26 21:05:20 -07:00
David Harris	812158aeee	Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each	2022-08-26 20:26:12 -07:00
David Harris	95dd50a567	Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem	2022-08-26 20:12:03 -07:00
Ross Thompson	db635e3ad2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 16:01:02 -05:00
David Harris	302a7fa294	Extended HADDR to PA_BITS	2022-08-25 13:11:36 -07:00
Ross Thompson	179aec3616	Still not working with rv32ic.	2022-08-25 15:03:54 -05:00
Ross Thompson	3b612d6201	Possible fixes for earily messup of rv32ic and rv64ic configs.	2022-08-25 14:42:08 -05:00
Ross Thompson	e605ef57dc	BROKEN. Don't use this commit. ... Issue running cacheless with bus.	2022-08-25 11:02:46 -05:00
Ross Thompson	b0aea77b20	Added generate around uncore.	2022-08-25 10:35:24 -05:00