David Harris
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a96d8dcec0
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removed fma directory, improved plic comments
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2023-01-18 13:06:54 -08:00 |
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David Harris
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dc74bcff5b
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Clean up tabs
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2023-01-15 18:23:09 -08:00 |
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David Harris
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be029deb07
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uncore cleanup
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2023-01-14 17:21:07 -08:00 |
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David Harris
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16ff590a8c
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uncore cleanup
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2023-01-14 17:09:11 -08:00 |
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David Harris
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b302f66baf
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uncore cleanup
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2023-01-14 17:07:36 -08:00 |
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David Harris
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ae7e7b57ec
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uncore cleanup
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2023-01-14 17:00:58 -08:00 |
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David Harris
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9ac905b5c0
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sdc cleanup
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2023-01-14 16:49:44 -08:00 |
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David Harris
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41c7d5c510
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uncore cleanup
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2023-01-14 06:15:35 -08:00 |
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David Harris
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7d93659f6b
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changed name to CORE-V-WALLY
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2023-01-11 15:15:08 -08:00 |
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David Harris
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b911056e66
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Changed Wally to CORE-V Wally
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2023-01-11 14:03:44 -08:00 |
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David Harris
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e92cffbb5e
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Changed MIT license to Solderpad License
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2023-01-10 11:35:20 -08:00 |
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David Harris
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9e67b9475e
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Remove unused signals
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2023-01-07 06:26:29 -08:00 |
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David Harris
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15b829bbf7
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Removed unused signals
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2023-01-07 06:06:54 -08:00 |
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Ross Thompson
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3fc121ef70
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Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.
Switched to even simplier PC+2/4 logic.
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2022-12-21 09:00:09 -06:00 |
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David Harris
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9133b3a7a4
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FPU remove unused signals
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2022-12-20 14:43:30 -08:00 |
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David Harris
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c26c3b76ea
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Renamed renamed sram to ram
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2022-12-20 08:36:45 -08:00 |
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Ross Thompson
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403434580d
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Fixed the uart transmit fifo overrun bug.
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2022-10-26 14:48:09 -05:00 |
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Jacob Pease
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160ca366c8
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Added PLIC signals for debugging on FPGA.
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2022-10-25 13:57:09 -05:00 |
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Ross Thompson
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9ba487c323
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Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
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2022-10-24 15:38:39 -05:00 |
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Ross Thompson
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7244ca1e7b
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Bit width error.
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2022-10-24 13:48:47 -05:00 |
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Jacob Pease
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b1170ec7a2
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Extended rxfifotimeout count to actually be 4 characters long.
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2022-10-20 17:35:49 -05:00 |
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Ross Thompson
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92accfb1a6
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Updated uart settings and fpga wave config.
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2022-10-18 15:05:33 -05:00 |
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Ross Thompson
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d81af3bca8
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Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
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2022-09-29 11:54:03 -05:00 |
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Ross Thompson
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66c45949b5
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Renamed brom1p1r to rom1p1r.
removed used file bram2p1r1w.sv.
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2022-09-21 12:31:20 -05:00 |
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Ross Thompson
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ac864a6ca3
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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Ross Thompson
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426ec6222b
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Added chip enables to sram.
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2022-09-20 10:49:14 -05:00 |
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Jacob Pease
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1e7bbe1a87
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Fixed rxfifotimeout restarting for every new character, even when already high.
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2022-09-19 18:00:30 -05:00 |
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Ross Thompson
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68a200d728
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Added generate around the longer latency version of the ram_ahb.sv
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2022-09-06 09:21:03 -05:00 |
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Ross Thompson
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2554f96662
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Cleaned up hacks to ram.
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2022-09-04 14:52:40 -05:00 |
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Ross Thompson
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c87268baf1
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Modified ram_ahb to work with different latencies.
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2022-09-04 14:46:15 -05:00 |
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Ross Thompson
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f9daa7f6b9
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Progress towards fixing the select HREADY muxing in uncore.
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2022-09-04 13:07:49 -05:00 |
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Ross Thompson
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4d60d9a840
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Fixed up FPGA constraints.
Added back in the fpga boot rom preload.
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2022-09-02 13:54:35 -05:00 |
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Ross Thompson
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122c88ee46
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Created two new pma regions for dtim and irom.
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2022-08-28 13:50:50 -05:00 |
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Ross Thompson
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5e63af5887
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Reordered the adrdecs.
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2022-08-28 13:38:57 -05:00 |
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David Harris
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f2517f8290
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Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
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2022-08-27 20:31:09 -07:00 |
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David Harris
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f0b4f69b65
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Added IROM and DTIM decoding to adrdecs
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2022-08-26 20:45:43 -07:00 |
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David Harris
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902d2067ba
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Removed delayed AHB signals from top level
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2022-08-25 15:34:14 -07:00 |
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David Harris
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302a7fa294
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Extended HADDR to PA_BITS
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2022-08-25 13:11:36 -07:00 |
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Ross Thompson
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ad485fe591
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 09:03:34 -05:00 |
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Ross Thompson
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701324eeb8
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Updated ila signals.
Improve fpga wave config.
added back in the fpga preload.
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2022-08-25 09:03:29 -05:00 |
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David Harris
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562be633ab
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Stripped write capaibilty out of rom_ahb
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2022-08-24 17:23:08 -07:00 |
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David Harris
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a131e1f17a
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Added ROM module and moved memories into generic/mem
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2022-08-24 17:03:22 -07:00 |
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David Harris
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6785644fb8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-24 16:30:28 -07:00 |
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David Harris
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b21b91234b
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Ram cleanup
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2022-08-24 16:30:25 -07:00 |
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Ross Thompson
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769af32f2a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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fc22e807e2
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Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
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2022-08-24 17:52:25 -05:00 |
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David Harris
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93d7d7179e
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Added parity and stop bit tests to UART
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2022-07-28 04:35:51 +00:00 |
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slmnemo
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ca4511b6dc
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Fixed UART FIFO bugs and added FIFO tests
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2022-07-22 17:13:19 -07:00 |
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David Harris
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d22587090b
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Reset MSR on read
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2022-07-22 04:29:27 +00:00 |
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slmnemo
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3d2c6683d8
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Fixed UART bug related to parity and MSR/LSR
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2022-07-21 20:35:46 -07:00 |
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