Ross Thompson
a4907b5d29
Lee Moore found another bug using imperas.
...
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
2023-02-02 23:52:21 -06:00
David Harris
c666015c56
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-01-31 14:40:19 -08:00
Ross Thompson
92fc532b82
Created scripts to install imperas and run a single test using imperas.
2023-01-31 13:51:05 -06:00
Ross Thompson
026071e247
Merge branch 'imperas'
2023-01-31 12:46:22 -06:00
David Harris
a2f66313ea
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-01-30 11:00:51 -08:00
Ross Thompson
cc48cdc97b
Imperas found a real bug in virtual memory.
...
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.
Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
2023-01-30 11:47:51 -06:00
David Harris
234860d4e5
Merged PR#37 branch predictor
2023-01-29 14:25:28 -08:00
Ross Thompson
a9a7054e2f
Merge branch 'main' of https://github.com/openhwgroup/cvw
...
This merges the branch predictor improvements into the main repo.
2023-01-29 15:24:20 -06:00
David Harris
be2dc6a774
Removed unused wally-harvard.do script
2023-01-29 11:34:35 -08:00
David Harris
5d2a48d5d8
Converted rv32ic to rv32imc
2023-01-29 11:33:54 -08:00
Ross Thompson
f93eaeef8e
Fixed another bug with the speculative gshare with instruction class prediction.
2023-01-29 00:33:40 -06:00
Ross Thompson
6371d91b37
Added another performance counter to track overall branch miss-predictions.
2023-01-28 17:50:46 -06:00
Ross Thompson
8a277f6b75
Possible fix for speculative gshare.
2023-01-28 16:14:19 -06:00
Ross Thompson
a212960352
Very hacky. But I think gshare is now correct with respect to repair on instruction class miss prediction.
2023-01-27 11:34:45 -06:00
David Harris
237e3a620f
Removed suggestion about make allclean
2023-01-27 05:57:05 -08:00
Ross Thompson
4fa2dcc2a5
Changed the performance counters to track different data.
...
Now rather than tracking jump(r) we track jump(r) and taken branches.
2023-01-26 13:21:28 -06:00
Ross Thompson
3dc441ff8c
Intermediate commit. Passes regression tests, but RAS is not correct.
2023-01-25 19:39:18 -06:00
Ross Thompson
5da1aeeef1
Improved RAS again.
2023-01-25 17:10:52 -06:00
David Harris
45218863af
test
2023-01-20 15:23:38 -08:00
Ross Thompson
5b5a615e4a
Integrated the missing zifence tests into the regression test.
2023-01-20 10:34:49 -06:00
eroom1966
d9d5b99218
update
2023-01-19 13:29:46 +00:00
eroom1966
7c0cad148d
Partial fix for misaligned LD/ST
2023-01-18 17:11:39 +00:00
eroom1966
2e4e5f9c61
changes made with Ross
2023-01-18 16:46:48 +00:00
eroom1966
a5a5b7a408
add im flags for compressed disass
2023-01-18 13:37:28 +00:00
eroom1966
c18942bd0b
refer to correct path
2023-01-18 13:26:07 +00:00
Ross Thompson
aa942feedc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2023-01-17 15:44:44 -06:00
David Harris
c73bea83cd
Clean up warnings from Questa
2023-01-17 13:43:39 -08:00
Ross Thompson
caff6e788c
Somehow the imperas files spilled into the main branch.
2023-01-17 15:39:34 -06:00
sarah-harris
4e9a7a6403
Changing signal name to ImmExtD/E to match figures
...
Changing signal name:
ExtImmD/E -> ImmExtD/E
to match figures.
2023-01-17 06:33:58 -08:00
eroom1966
f4e7e54abe
Code refactor and addition of rvvi interface
2023-01-17 12:47:38 +00:00
David Harris
f93b7cfda7
Removed Imperas tests from regression
2023-01-16 07:01:07 -08:00
David Harris
12e12e464a
Makefile and setup cleanup
2023-01-15 20:27:12 -08:00
Ross Thompson
3cc37e3f12
Completely stripped down imperas simulation.
...
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
2023-01-12 12:48:38 -06:00
Ross Thompson
5ad0bacf5b
Created separate imperas testbench.
...
Resolved logger issue with the duplicated instructions after commit.
2023-01-12 12:07:07 -06:00
Ross Thompson
6cbce9672d
Possibly working speculative global history.
2023-01-08 23:46:53 -06:00
Ross Thompson
0eda4b1ab3
core part of global history works now. forwarding is still broken.
2023-01-08 23:35:02 -06:00
Ross Thompson
78e441fb38
More branch predictor cleanup.
2023-01-05 17:19:27 -06:00
Ross Thompson
9d03109f34
Officially added global history with speculation to types of branch predictors.
2023-01-05 14:04:09 -06:00
Ross Thompson
0eceeeeeaa
Simiplified global history branch predictor.
2023-01-04 23:41:55 -06:00
David Harris
fb0b2d4227
Moved floating-point tests earlier in Wally config
2022-12-25 22:31:20 -08:00
Ross Thompson
6e9d1eb180
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-23 19:51:23 -06:00
Katherine Parry
4b50ffac91
reworked negitive sticky bit handeling in fma
2022-12-23 17:01:34 -06:00
Ross Thompson
a2de53aeeb
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
David Harris
9e21358d75
Removed unused signals from FPU
2022-12-23 00:18:39 -08:00
David Harris
56312cd0a6
Clean up unused FPU signals
2022-12-22 23:53:09 -08:00
Ross Thompson
2cc4d66ded
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
206bc7daa6
Closing in on icache flushed by FlushD rather than TrapM.
2022-12-22 20:19:09 -06:00
Ross Thompson
b1475df5e1
Wavefile updates.
2022-12-22 19:45:02 -06:00
Ross Thompson
a02b40cf02
Changes to wave file.
2022-12-21 08:41:47 -06:00
David Harris
dd0a02f0c8
Converted tvecmux to structural
2022-12-20 16:24:04 -08:00
