David Harris
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f5dab9f2fe
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Check for legal SATP mode values
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2023-08-24 05:18:04 -07:00 |
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Ross Thompson
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00e65c4ae7
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Oups there was a bug in the SATP fix. RV32GC was broken by the changes.
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2023-08-23 09:42:46 -05:00 |
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Jacob Pease
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140d246fb5
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Prevented writes to SATP enabling SV57. This follows the spec more accurately. Linux can now successfully probe SATP.
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2023-08-22 16:25:56 -05:00 |
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Ross Thompson
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7e06775135
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Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop.
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2023-07-28 11:20:29 -05:00 |
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David Harris
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b6ae5661b4
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Added environment configuration control (menvcfg/senvcfg) of cbo instructions
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2023-07-02 01:52:25 -07:00 |
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Harshini Srinath
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3593762cfa
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Merge branch 'main' into main
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2023-06-14 11:52:45 -07:00 |
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Harshini Srinath
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3f8cd8932c
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Update csrs.sv
Program clean up
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2023-06-13 22:16:43 -07:00 |
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Harshini Srinath
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120cde2aea
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Update csrs.sv
Program clean up
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2023-06-12 19:53:41 -07:00 |
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David Harris
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b70b0c7c5e
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Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
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2023-06-09 14:40:01 -07:00 |
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Ross Thompson
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c7e515634d
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I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types.
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2023-05-26 13:56:51 -05:00 |
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Ross Thompson
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8cf38b28aa
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The privileged unit is parameterized using Lim's method.
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2023-05-26 12:03:46 -05:00 |
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David Harris
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da53f240d3
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Refactored InstrValidNotFlushed into CSR Write signals
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2023-03-30 17:06:09 -07:00 |
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David Harris
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406bb22b6a
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Started factoring out InstrValidNotFlushed from CSRs
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2023-03-30 14:56:19 -07:00 |
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Kip Macsai-Goren
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3805cf993a
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unnecessary comments cleanup
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2023-03-29 19:32:57 -07:00 |
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Kip Macsai-Goren
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491ef14b71
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Resolved ImperasDV receiving incorrect cause values
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2023-03-29 15:04:56 -07:00 |
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David Harris
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9d8f9e4428
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Reduced number of bits in mcause and medeleg registers
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2023-03-29 07:02:09 -07:00 |
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David Harris
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2e238c15aa
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CSRS privileged coverage test
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2023-03-28 04:37:56 -07:00 |
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Ross Thompson
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46b1bca4fc
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Fixed all tap/space issue in RTL.
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2023-03-24 17:32:25 -05:00 |
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David Harris
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121d1cea62
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Added csrwrites.S test case for privileged tests
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2023-03-23 10:55:32 -07:00 |
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David Harris
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80fc851332
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Fix Issue #142: SCOUNTEREN powers up at 1 instead of 0
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2023-03-22 04:41:57 -07:00 |
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David Harris
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4cde207958
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Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression.
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2023-03-18 10:10:58 -07:00 |
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Kip Macsai-Goren
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a38f7cc8a1
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added reset values to stime and stimecmp registers
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2023-03-04 15:06:15 -08:00 |
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David Harris
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fe161f6bde
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Fixed missing assign when SSTC is not supported
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2023-02-26 07:12:13 -08:00 |
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David Harris
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8895114152
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Fixed SSTC being unusable in M-MODE without Status.TM. Disable STIMECMP registers when SSTC_SUPPORTED = 0
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2023-02-26 06:30:43 -08:00 |
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David Harris
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5b370bdc0f
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Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass.
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2023-02-16 07:37:12 -08:00 |
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David Harris
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78eb90715c
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Removed pipelined level of hierarchy
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2023-02-02 14:14:11 -08:00 |
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