Noah Boorstin
c42c485377
busybear: instantiate soc instead of hart
2021-02-23 18:59:06 +00:00
kaveh pezeshki
e146946e58
Merge remote-tracking branch 'origin/tlb_toy' into busybear
2021-02-22 02:23:01 -08:00
Thomas Fleming
ca51e7ca1c
Create simple TLB
...
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
2021-02-18 18:06:09 -05:00
David Harris
fe7299c155
Resotred part of multiplier for lab 2
2021-02-17 16:14:04 -05:00
David Harris
492ec0ee78
Removed multiplier for lab 2
2021-02-17 16:06:16 -05:00
David Harris
e8d3c7d9e7
Multiplier tweaks
2021-02-17 16:00:27 -05:00
David Harris
e64e8afb7f
Started to integrate OSU divider
2021-02-17 15:38:44 -05:00
David Harris
a7dd20b388
Multiply instructions working
2021-02-17 15:29:20 -05:00
Noah Boorstin
43f9abdbed
busybear testbench: check (almost) all the CSRs
2021-02-16 20:03:24 -05:00
David Harris
adc5d5bc1a
Added MUL
2021-02-15 22:27:35 -05:00
David Harris
3900abeb86
WALLY ALU tests
2021-02-15 10:16:31 -05:00
Domenico Ottolia
3ee975dd5a
Add privileged test cases
2021-02-14 17:01:46 -05:00
Shreya Sanghai
4e887f83a3
added branch tests
2021-02-12 22:40:08 -05:00
Noah Boorstin
84d856d1e5
busybear: allow testbench to ignore lack of MMU for now
...
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing
If it is, we're at 1M instructions!
2021-02-12 20:08:56 +00:00
Noah Boorstin
dd3a5b74a1
busybear: slightly neater error handling
2021-02-12 17:21:56 +00:00
bbracker
deb7780897
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Noah Boorstin
79fb83409f
bump into virtual/physcial memory?
2021-02-11 23:06:12 -05:00
Noah Boorstin
e89af96bc0
busybear: more updates
...
now gets to instruction 839037 before failing
also updates to match new gdb output format
umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
2021-02-11 22:42:58 -05:00
Tejus Rao
fb6a4bbbf0
added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
2021-02-11 13:38:38 -05:00
Teo Ene
5f84ed407c
Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
2021-02-10 20:48:39 -06:00
ethan-falicov
7925fe3131
Fixed merge conflict stuff
2021-02-10 10:03:30 -05:00
ethan-falicov
06517631cc
More merge conflicts yay
2021-02-10 09:54:30 -05:00
ethan-falicov
863796b3c1
Merge conflict fixing
2021-02-10 09:45:47 -05:00
ethan-falicov
67662b888e
Adding I Type test cases from Lab 1
2021-02-10 09:39:43 -05:00
Jarred Allen
e334475ab5
Fix compile error in imperas testbench
2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
805817cda4
merge conflict?
2021-02-07 02:34:49 -05:00
Noah Boorstin
01b1b1705d
Busybear: next week of updates
...
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
- parsed first 1M instructions, and now parse from split GDB runs
- now at about 230k instructions, can't progress further for now since atomic instructions
aren't implemented yet
2021-02-07 03:14:48 +00:00
Jarred Allen
29b7a0cd25
Actually run the WALLY-LOAD tests
2021-02-06 14:56:40 -05:00
Jarred Allen
a3f2f4c7bc
Add test vector set for load instructions
2021-02-06 13:05:59 -05:00
bbracker
15c0b4af22
JAL testing
2021-02-05 08:08:42 -05:00
Noah Boorstin
c03f69fb80
Change CSR reset and available bits to conform to OVPsim
...
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
2021-02-04 22:03:45 +00:00
Thomas Fleming
8d7a515ae7
Complete STORE tests
2021-02-04 15:38:22 -05:00
Noah Boorstin
fc734eb14e
busybear: add more CSRs
2021-02-04 20:13:36 +00:00
Noah Boorstin
77a88d8019
busybear: check initial values also
2021-02-04 19:22:09 +00:00
Brett Mathis
11e2666bb2
Parallel FSR's and F CTRL logic
2021-02-04 02:25:55 -06:00
Jarred Allen
088fbbcbf0
Change busybear test to use work-busybear library
2021-02-03 11:12:47 -05:00
Jarred Allen
f700efc2b3
Start on a test set for loads
2021-02-03 00:37:43 -05:00
David Harris
2a80bcf543
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 19:44:43 -05:00
David Harris
756352f129
Minor tweaks
2021-02-02 19:44:37 -05:00
Jarred Allen
e5bd749e2a
Refactor regression test
2021-02-02 17:22:29 -05:00
Noah Boorstin
d2064987e9
Add busybear testbench to nightly regression checking
...
If you don't like how I did this please feel free to undo it
2021-02-02 22:05:35 +00:00
Noah Boorstin
b5f474d9f5
same thing but do that right this time
2021-02-02 21:47:15 +00:00
Noah Boorstin
6dd5c42d55
change undefined syntax in extend.sv
...
don't need verilator execption anymore
2021-02-02 21:39:20 +00:00
David Harris
429f48e766
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
9f9c3bcece
Changed DTIM latency to 2 cycles
2021-02-02 14:22:12 -05:00
David Harris
616830a3f0
Cleaned up hazard interface
2021-02-02 13:53:13 -05:00
David Harris
587a343dac
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 13:42:35 -05:00
David Harris
229bde5953
Moved LoadStall generation to IEU
2021-02-02 13:42:23 -05:00
David Harris
bb83fda1d8
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
Jarred Allen
da43b2be53
Fix intermittent errors caused by weird library stuff
2021-02-02 11:20:09 -05:00
